• Senior Systems Design Engineer , Geo

    Google (Mountain View, CA)
    Senior Systems Design Engineer , Geo _corporate_fare_ Google _place_ Mountain View, CA, USA ** Mid ** Experience driving progress, solving problems, and ... with product and program management, manufacturing, and PLM teams will define top- level design requirements and communicate the consequences of design… more
    Google (09/30/25)
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  • Building Automation Design Engineer

    Siemens (Cypress, CA)
    …+ High school diploma or state-recognized GED + Experience in building automation (HVAC controls) design : + Mid - Level : 3+ years + Senior Level : 5+ ... to increase customer satisfaction and job profitability. **As a Building Automation Design Engineer you will:** + Understand project requirements and design … more
    Siemens (10/03/25)
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  • Senior CPU Physical Design Engineer…

    Google (Mountain View, CA)
    Senior CPU Physical Design Engineer , Silicon _corporate_fare_ Google _place_ Austin, TX, USA; Mountain View, CA, USA ** Mid ** Experience driving progress, ... practical experience. + 5 years of experience with physical design flow such as constraints, synthesis, floor planning, place...+ benefits. Our salary ranges are determined by role, level , and location. Within the range, individual pay is… more
    Google (10/01/25)
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  • CAD/PCB Design Engineer , Pixel…

    Google (Mountain View, CA)
    CAD/PCB Design Engineer , Pixel Phones _corporate_fare_ Google _place_ Mountain View, CA, USA ** Mid ** Experience driving progress, solving problems, and ... 2 years of experience in Printed Circuit Board (PCB) design and Flexible Printed Circuit (FPC) design ,...+ benefits. Our salary ranges are determined by role, level , and location. Within the range, individual pay is… more
    Google (10/01/25)
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  • Physical Design Flow and Methodology…

    Google (Sunnyvale, CA)
    Physical Design Flow and Methodology Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA ** Mid ** Experience driving progress, solving problems, and ... in a semiconductor environment. + Experience developing automated physical design workflows from RTL to GDS, utilizing Tcl, Python,...+ benefits. Our salary ranges are determined by role, level , and location. Within the range, individual pay is… more
    Google (09/28/25)
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  • ASIC Design Verification Engineer…

    Google (Mountain View, CA)
    ASIC Design Verification Engineer , Devices and Services _corporate_fare_ Google _place_ Mountain View, CA, USA ** Mid ** Experience driving progress, solving ... unparalleled performance, efficiency, and integration. As an Application-Specific Integrated Circuit (ASIC) Design Verification Engineer , you will be part of a… more
    Google (10/04/25)
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  • Design Verification Engineer

    Google (Mountain View, CA)
    Design Verification Engineer _corporate_fare_ Google _place_ Mountain View, CA, USA; San Diego, CA, USA ** Mid ** Experience driving progress, solving ... equivalent practical experience. + 4 years of experience in silicon design verification. + Experience developing and maintaining verification testbenches, test… more
    Google (10/07/25)
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  • Plumbing Design Engineer…

    Legence (Irvine, CA)
    …- 3 days in-office, 2 days remote Salary Range: $120,000-$150,000, based on experience Career Level : Mid - level Location: Long Beach, CA or Irvine, CA General ... Los Angeles, and San Jose. P2S has an exciting opportunity for a Plumbing Engineer with 5+ years of experience designing plumbing systems for new buildings and… more
    Legence (10/08/25)
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  • Quantum Device Design Engineer…

    Google (Mountain View, CA)
    Quantum Device Design Engineer , Quantum AI _corporate_fare_ Google _place_ Goleta, CA, USA; Mountain View, CA, USA ** Mid ** Experience driving progress, ... Quantum Integrated Circuit Designer, you will support the physical design of quantum processors and associated analog, DC, and...+ benefits. Our salary ranges are determined by role, level , and location. Within the range, individual pay is… more
    Google (10/01/25)
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  • ASIC Engineer , IP Design , Silicon

    Google (Mountain View, CA)
    ASIC Engineer , IP Design , Silicon _corporate_fare_ Google _place_ Mountain View, CA, USA ** Mid ** Experience driving progress, solving problems, and mentoring ... practical experience. + 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture. + Experience with...+ benefits. Our salary ranges are determined by role, level , and location. Within the range, individual pay is… more
    Google (10/03/25)
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