• Senior ASIC Design Verification…

    Google (Sunnyvale, CA)
    …at RTL using SystemVerilog for ASICs. + Experience in memory subsystem design verification. + Experience in Power aware verification, Gate level simulations, and ... Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that… more
    Google (04/25/25)
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  • Physical Design Engineer , TPU

    Google (Sunnyvale, CA)
    …related field, or equivalent practical experience. + 7 years of physical design experience with industry-standard tools, languages, and methodologies relevant to the ... + Experience with compute cores, high-speed memory technologies, silicon interposer design and advanced packaging technologies. + Experience crafting physical … more
    Google (04/02/25)
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  • DSP or Serdes RTL Lead Digital Design…

    Cadence Design Systems, Inc. (San Jose, CA)
    …front-end coding, scripting and developing flows at all phases of the digital design and functional verification. It is further expected that the candidate will be ... able to work as part of a small and focused team of engineers...application teams. Candidate should be willing to work full time in the San Jose office. A Cadence satellite… more
    Cadence Design Systems, Inc. (02/06/25)
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  • Senior System Design Engineer , SSD…

    SanDisk (Milpitas, CA)
    …quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities ... of the role focus on validation of memory system design on Sandisk's enterprise SSD products + In-depth understanding...range of possible compensation for this role at the time of this posting. We may ultimately pay more… more
    SanDisk (04/05/25)
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  • Physical Design /PDK methodology…

    Applied Materials (Santa Clara, CA)
    …produce virtually every new chip and advanced display in the world. We design , build and service cutting-edge equipment that helps our customers manufacture display ... best, brightest, and most talented people in the world who work together as part of a winning team. **Key Responsibilities** + Expertise in PDK enablement and… more
    Applied Materials (03/25/25)
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  • R&D Engineer IC Design

    Broadcom (Irvine, CA)
    …position is responsible for, but not limited to, the following job duties: + Work as part of a physical design team implementing chips from netlist to GDSii with ... **Please Note:** **1. If you are a first time user, please create your candidate login account...good understanding of the technology elements as well as design flow in all stages. + Responsible for floorplanning,… more
    Broadcom (03/06/25)
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  • ASIC Design Engineer , Platform IP,…

    Google (Mountain View, CA)
    …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or ... RTL code, performance and power as well as low-power design techniques. + Experience with ARM-based SoCs, interconnects and...for RTL quality checks (eg, Lint, CDC, RDC). Be part of a team that pushes boundaries, developing custom… more
    Google (04/10/25)
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  • SoC Physical Design Engineer…

    Google (Mountain View, CA)
    …of Circuit design , device physics and deep sub-micron technology. Be part of a team that pushes boundaries, developing custom silicon solutions that power ... practical experience. + 4 years of experience in Physical Design . + Experience in one or more synthesis/PnR tools...and integration. The US base salary range for this full- time position is $132,000-$189,000 + bonus + equity +… more
    Google (03/29/25)
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  • ASIC Design Verification Engineer

    Broadcom (Irvine, CA)
    **Please Note:** **1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)** **2. If ... you apply.** **Job Description:** **_Would you like to become part of a stable team developing silicon products for...are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs… more
    Broadcom (04/29/25)
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  • ASIC Engineer , IP Design , Silicon

    Google (Mountain View, CA)
    …or equivalent practical experience. + 5 years of experience with RTL design using Verilog/System Verilog and microarchitecture. + Experience with a scripting ... architecture. + 8 years of industry experience with IP design . + Experience with methodologies for low power estimation,...for RTL quality checks (eg, Lint, CDC, RDC). Be part of a team that pushes boundaries, developing custom… more
    Google (04/02/25)
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