- Google (Sunnyvale, CA)
- …its integration within AI/ML-driven systems. As a Signal Integrity/ Power Integrity Engineer , you will lead chip and package design , ensuring optimal Signal ... Signal and Power Integrity Engineer , PhD, University Graduate..., software, and vendors. You will drive signal and power design implementations on chip and advanced… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical design ... of an end-to-end IP or integration of ASIC/SoC design and point out lower power and...congestion/timing issues and implement functional ECO's 7. Use EDA tool -based programming and scripting techniques to automate and improve… more
- Meta (Sunnyvale, CA)
- …the efficiency and innovation of our data center applications. **Required Skills:** ASIC Engineer Physical Design Responsibilities: 1. Develop and own physical ... design implementation of multi-hierarchy low- power and high-performance designs, including physical-aware logic synthesis, floorplan, place and route, clock tree… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... be doing: + Work on crafting creative Signal and Power Integrity solutions to complex system design ...dynamic clocking and throttling. + Familiarity with the SIMPLIS tool for regulator modeling; experience in modeling the behavior… more
- NVIDIA (Santa Clara, CA)
- …can make a lasting impact on the world. We are now looking for a Senior Power Integrity Methodology CAD Engineer . What you'll be doing: + Developing physical ... are needed for NVIDIA chips. + Crafting workflows and tool methodologies for power and noise analysis...of EMIR analysis and signoff. + Familiar with hierarchical design approach and hierarchical signoff. + Experience with shift-left… more
- SpaceX (Sunnyvale, CA)
- …hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer /Senior: $170,000.00 - $230,000.00/per year Your actual level and ... Sr. SOC/ASIC Physical Design Methodology/CAD Engineer (Silicon Engineering) Sunnyvale,...flows PREFERRED SKILLS AND EXPERIENCE: + Experience in high-performance, low- power physical design , and implementation techniques with… more
- Celestica (San Diego, CA)
- …logger, IR camera, wind tunnel, air speed meter etc. + Advanced knowledge of Mechanical design tool such as Pro/E considered a plus. + Advanced knowledge of ... drive to find the way for our customers. Let's engineer the future together. Responsible for architecting, implementing, and...and memory. You will work with HW and FW design , mechanical, power , and validation engineers. You… more
- Amazon (Cupertino, CA)
- …and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and ... flow development and support. Preferred Qualifications - Expertise in high-performance, low- power physical design , and implementation techniques with industry… more
- NVIDIA (Santa Clara, CA)
- …make a lasting impact on the world. We are now looking for a Senior Power Integrity Methodology Engineer . What you'll be doing: + Developing physical design ... for NVIDIA chips. + In addition, you'll participating and developing flow and tool methodologies power and noise analysis across multiple projects. What we… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... + Work on crafting creative Signal Integrity solutions to complex system design problems. + Modeling and Optimization of vias, connectors, sockets, breakouts and… more