• Physical Design Engineer

    Qualcomm (Santa Clara, CA)
    …involved in all critical decisions for Block level Physical Implementation. Experience in low power physical design with ICC2/FC tool set, good debugging and ... Wireless Technology team you will be working on low power next generation Wifi subsystem related Physical design...Requirements: - 2+ yrs. of working experience in physical design with ICC2/FC tool set from netlist… more
    Qualcomm (05/03/25)
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  • Senior Physical Design Methodology…

    NVIDIA (Santa Clara, CA)
    …inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer (s) to join our outstanding Networking Silicon ... for NVIDIA chips. + Participate in developing flow and tool methodologies for chip floorplan, power and...Design Engineering + Familiar with aspects of chip design including Floor planning, Clock and Power more
    NVIDIA (03/11/25)
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  • Senior Physical Design Methodology…

    NVIDIA (Santa Clara, CA)
    …of power intent files such as UPF, and use of FSDB/SAIFs for power optimization + Understanding of hierarchical design , pinning and budgeting flows + ... + Work with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions...Experience with power distribution networks, Design for Yield and Manufacturability, EM and IR closure… more
    NVIDIA (02/20/25)
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  • ASIC Design Engineer

    Broadcom (San Jose, CA)
    …skill Other highly desirable experience: o 802.3 Ethernet or NIC experience. o Low power design skills o Layer 1 through Layer 4 experience The candidate ... , verification, and synthesis. Must have strong UNIX-based EDA tool skills and knowledge of ASIC design flows. Must be familiar with reusable HDL coding styles… more
    Broadcom (04/26/25)
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  • CPU Physical Design Pathfinding…

    Qualcomm (San Diego, CA)
    …Pathfinding Engineer , you will work with Architecture, RTL, Physical Design , Circuits, CAD and Post-Silicon teams to lead the cutting-edge technology development ... to be implemented in the next generation CPUs to meet aggressive Power , Area and Performance goals. Must have skill/experience + Experience with Synthesis, place and… more
    Qualcomm (04/03/25)
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  • Senior Physical Design Methodology…

    NVIDIA (Santa Clara, CA)
    …experience in Physical Design Engineering + Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, ... part of the global circuits team at NVIDIA that design the state-of-the-art GPUs for all applications such as...driving cars. Come join us in our mission to Engineer the next generation of best-in-class products. Our teams… more
    NVIDIA (04/19/25)
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  • Principal Silicon Circuits System Design

    NVIDIA (Santa Clara, CA)
    …silicon in brand-new process technologies to characterize and optimize performance, power , yield, and quality for groundbreaking products. + Build pre and ... and silicon features, correlate silicon behavior with simulations, and provide design feedback. + Driving new feature initiatives across multiple business units,… more
    NVIDIA (04/15/25)
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  • UX Design Engineer / AI Creative…

    US Tech Solutions (Mountain View, CA)
    …awe-inspiring prototypes. You possess a deep understanding of AI/ML capabilities and embrace a design process that leverages AI as a tool for exploration and ... **Responsibilities:** + Rapid Prototyping: Develop high-fidelity prototypes that demonstrate design intent, technical feasibility, and the potential power more
    US Tech Solutions (04/18/25)
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  • NoC Interconnect Design Engineer

    Qualcomm (San Diego, CA)
    …team with design guidelines for bus protocol compliance and best power interconnect. Candidates should have strong knowledge of bus protocols, synthesis tools, ... and drive micro-architecture choices using performance and power analysis, and to provide the SoC...process nodes, VLSI design , and successful industry experience with deployment of IPs… more
    Qualcomm (05/13/25)
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  • Analog/Mixed Signal ASIC Design

    Qualcomm (San Diego, CA)
    …Technologies, Inc. **Job Area:** Engineering Group, Engineering Group > Analog Mixed Signal Design **General Summary:** QCT Mixed-Signal IP (MSIP) design team is ... circuit designers at various levels to help with designing high-performance and low- power mixed-signal IPs (SerDes, DDR, PLL, DAC, ADC, sensors, etc.) in advanced… more
    Qualcomm (04/23/25)
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