- NVIDIA (Santa Clara, CA)
- …see how you can make a lasting impact on the world. We are seeking a Senior Software Engineer to join our Software Infrastructure Team in Santa Clara, CA. This ... scale. What you'll be doing: + Contribute to the design and development of a scalable, robust, and reliable...salary range is 200,000 USD - 322,000 USD for Level 5, and 248,000 USD - 391,000 USD for… more
- Warner Bros. Discovery (San Francisco, CA)
- …A24, and more. Turn your streaming obsession into a career- we're hiring! ** Senior MLE, Personalization, Content Discovery** Every great story has a new beginning. ... You:** We are looking for a passionate Machine Learning Engineer to build and scale the DTC personalization models...conception to completion + Author, test, review, and optimize production- level code in Python, Go and Java while executing… more
- RTX Corporation (El Segundo, CA)
- …all mission areas at Raytheon. Our department is currently hiring for a ** Senior Modeling Analysis & Simulation Operations Engineer ** to develop, analyze, and ... operations), develop tools and methods to evaluate campaign, mission, and system level analysis and visualizations based on customer requirements. **This is an… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is searching for outstanding senior system software engineer to join the NVIDIA's automotive display driver team and help produce the next-gen ... in the segment. What you'll be doing: + Define, design , develop, test and maintain our GPU/Display kernel mode...salary range is 184,000 USD - 287,500 USD for Level 4, and 224,000 USD - 356,500 USD for… more
- JPMorgan Chase (San Francisco, CA)
- …direct and meaningful impact in a space designed for top performers. As a Senior Lead Security Engineer at JPMorganChase within the Cybersecurity and Technology ... + Facilitates security requirements clarification for multiple networks to enable multi- level security to satisfy organizational needs + Be responsible for triaging… more
- NVIDIA (Santa Clara, CA)
- We are looking to hire a System Test Engineer with a strong background in embedded and automotive systems with RF (Bluethooth and Wifi)system focus who will work in ... growing team today! What you will be doing: + Design , develop, and implement manufacturing test solutions for embedded...and accuracy + Troubleshoot and debug complex RF and system- level issues, c ollaborate with cross-functional teams to ensure… more
- Northrop Grumman (Manhattan Beach, CA)
- …making history. Northrop Grumman Defense Systems is seeking a **Principal / Sr Principal Design Engineer ** . This position is located in **Roy UT, Huntsville AL, ... be filled at either a Principal or Sr. Principal Engineer level . **What You'll Get to Do:**...and requirements management + Experience in defense system/subsystem product design Primary Level Salary Range: $86,600.00 -… more
- NVIDIA (Santa Clara, CA)
- …the field has expanded to encompass video games, movie production, product design , medical diagnosis and scientific research. Today, visual computing is becoming ... team! We are looking for a Software Security Compiler Engineer ! NVIDIA's invention of the GPU 1999 sparked the...at the center of deep-learning compiler technology spanning architecture design and support through functional languages. + Work with… more
- NVIDIA (Santa Clara, CA)
- We are looking for an experienced LLVM Compiler Engineer for an exciting and fun role in our GPU Software organization. We deliver features and improvements to ... from you! What you'll be doing: + Work on design and implementation of significant parts of the compiler....are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want… more
- Broadcom (San Jose, CA)
- …Sign-In before you apply.** **Job Description:** **Broadcom is looking for a senior level ASIC physical design engineer . In this highly visible role, you ... Computer Engineering with 6+ years of experience in Physical design .** + **Deep knowledge about industry standards in Physical...to debug LVS/DRC issues at the chip and block level .** + **Experience with CDC, static timing analysis methodologies… more