- Meta (Sunnyvale, CA)
- …introduction, new technology introduction, product launch and post-launch testing. As a Design Verification Engineer , you will require working closely with a ... plans, drive test execution and data collection. **Required Skills:** Mechanical Design Verification Engineer Responsibilities: 1. Define mechanical verification… more
- SpaceX (Sunnyvale, CA)
- …efforts to resolution + Work with EDA tool vendors to evaluate new tools , solve bugs, improve usability, methodology and design flow + Integrate foundry EDA ... hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer /Senior: $170,000.00 - $230,000.00/per year Your actual level and… more
- Amazon (Cupertino, CA)
- …and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and ... Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers...flows/methodologies for PPA and TAT improvements Work with EDA tool vendors to evaluate new methods, resolve bugs, improve… more
- Philips (San Diego, CA)
- **Sr. Software Design Assurance Engineer ** **In this role you** Will support New Product Development and Sustaining projects within Image Guide Therapy with ... respect to software, firmware, and hardware from a Software Design Quality Assurance perspective. **Your role:** + Develop and Review SW Design Verification… more
- Meta (Sunnyvale, CA)
- …from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement ... Design Verification improvements using the latest verification methodologies, tools and technologies from the industry **Minimum Qualifications:** Minimum… more
- Meta (Sunnyvale, CA)
- …from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement ... verification 2. Develop functional tests based on verification test plan 3. Drive Design Verification to closure based on defined verification metrics on test plan,… more
- US Tech Solutions (Santa Clara, CA)
- …- Language Skills **The Role:** + We are looking for an adaptive, self-motivative Design Verification Engineer to join our growing team.As a key contributor, you ... be on Camera **Top Must Have Skills:** + Solid minimum 8 + years Design Verification Experience + Verification Experience with DDR5 Controller /PHY + System Verilog… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …the world of technology. Are you looking to re-enter the workforce as a Physical Design Application Engineer after taking a career break for caregiving? Who is ... and have a minimum of three years of Physical Design work experience. This role is not open to...program, you will work with best in class EDA tools , collaborate with R&D and the Sales team in… more
- BAE Systems (San Diego, CA)
- …self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL + Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) + Proven ... may be available based on position level and/or job specifics. **Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)** **117193BR** EEO Career… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position ... various IPs, create functional test plans, and verify using advanced verification tools , flows and methodologies. + Build and reform world class verification… more