• ASIC Engineer , Design

    Meta (Menlo Park, CA)
    …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture ... in test plan development and debug. 5. Collaboration with implementation team to close the design on...Collaboration with implementation team to close the design on timing and power. **Minimum Qualifications:** Minimum Qualifications:… more
    Meta (04/09/25)
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  • Senior Software Engineer - C/C++, Qt,…

    Siemens (Fremont, CA)
    …Req ID: 446255 Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop ... the increasingly complex world of chip, board, and system design . We are seeking a passionate and highly skilled...We are seeking a passionate and highly skilled software engineer to join the Questa Visualizer Debug R&D team… more
    Siemens (03/04/25)
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  • Senior Principal Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …improved / drive timing to closure. + The position will interact with both Front End ( Design / DFT) and Back End Implementation Teams (P&R). + Proficient in STA ... the next Palladium Emulation ASIC and system at Cadence Design System. Palladium has been the leader in the...and Timing Closure. + Familiar with ECO techniques and implementation . + Maintain scripts and methodologies for analysis and… more
    Cadence Design Systems, Inc. (04/17/25)
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  • Senior Mixed Signal Design Engineer

    NVIDIA (Santa Clara, CA)
    …silicon validation, debugging, characterization and bring up. What you'll be doing: + Lead design and implementation of high speed interface circuit + Design ... of our Mixed Signal team, you will lead the design of CMOS high-speed interface circuits and mixed-signal circuits.... in deep submicron CMOS + Take designs through implementation and productization + Work with multi-functional teams What… more
    NVIDIA (03/13/25)
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  • IC Design Engineer

    Broadcom (San Jose, CA)
    …responsible for various key tasks in the areas of uArch and RTL design of cutting-edge network switch/routing Datapath designs. The day-to-day tasks for this ... not limited to the following: 1). Defining in the microarchitecture and implementing design of datapath for L2/L3 Network Switching and routing ASICs and various… more
    Broadcom (04/18/25)
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  • Physical Design Methodology Engineer

    quadric.io, Inc (Burlingame, CA)
    … + Proficiency in TCL scripting + Proficiency in chip front-end and back-end implementation tools such as Design Compiler, PrimeTime, ICC2 & Fusion Compiler. + ... What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing physical design more
    quadric.io, Inc (03/11/25)
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  • ASIC Engineer , Design

    Meta (Sunnyvale, CA)
    …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... in test plan development and debug 6. Collaboration with implementation team to close the design on...Collaboration with implementation team to close the design on timing and power **Minimum Qualifications:** Minimum Qualifications:… more
    Meta (04/03/25)
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  • Senior ASIC Design Verification…

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position ... to meet the unique demands of custom designed IPs. + Engage in design specification development by participating in discussions on architecture, intent, and … more
    NVIDIA (03/06/25)
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  • Full Chip CAD and Analog Design

    Google (Fremont, CA)
    …or equivalent practical experience. + 8 years of experience with analog circuit design principles and techniques. + Experience with analog design tools and ... Master's degree in Electrical Engineering or Computer Science. + Experience in logic design and UVM based simulation. + Experience in creating timing library models… more
    Google (05/03/25)
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  • GPU Design Integration Engineer

    Qualcomm (San Diego, CA)
    …understanding of multi clock design concepts + Familiarity with low power design + Experience in functional ECO implementation + Experience in Synthesis and ... the designer will be responsible for architecture and micro-architecture design of the ASIC, RTL design and...and micro-architecture design of the ASIC, RTL design and synthesis, logic and timing verification. Complex IP… more
    Qualcomm (05/01/25)
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