• Physical Design Flow and Methodology…

    Google (Sunnyvale, CA)
    …Physical Design EDA CAD tool workflows for ASIC development. + Collaborate with chip design teams to implement tools and methodologies for physical design ... in a semiconductor environment. + Experience developing automated physical design workflows from RTL to GDS, utilizing Tcl, Python,...focus on TPU architecture and its integration within AI/ML-driven systems . In this role, you will be a part… more
    Google (08/08/25)
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  • Design Verification Engineer

    Meta (Sunnyvale, CA)
    …the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with ... the testing infrastructure to validate new core IP or System on Chip (SoC) implementations. You will...state of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with… more
    Meta (08/01/25)
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  • Silicon Engineer , Digital Design

    Google (Mountain View, CA)
    design methodologies for clock domain checks, reset checks, and low power design . + Experience in collaborating with system and hardware architecture, ... field. + 5 years of experience with digital logic design principles and RTL design concepts. +...at least one of these areas: CPU Processor Cores, Buses/Fabric/Network-on-a- Chip , Debug/Trace, Interrupts, or Clocks/Reset. Be part of a… more
    Google (08/08/25)
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  • ASIC Design Engineer , Cloud-Scale…

    Amazon (Cupertino, CA)
    …career-advancing resources here to help you develop into a better-rounded professional. Custom SoCs ( System on Chip ) live at the heart of AWS Machine Learning ... Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers...and Be Curious" mindset About the team Custom SoCs ( System on Chip ) live at the heart… more
    Amazon (06/18/25)
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  • Staff RFIC Design Engineer

    Skyworks (Irvine, CA)
    Staff RFIC Design Engineer Apply now " Date:Jul 30, 2025 Location: Irvine, CA, US Company: Skyworks If you are looking for a challenging and exciting career in ... CaliforniaNearest Secondary Market:Los Angeles Job Segment: Network, Telecom, Telecommunications, Design Engineer , Front End, Technology, Engineering Apply now… more
    Skyworks (07/09/25)
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  • Sr. ASIC Design Engineer

    Amazon (Cupertino, CA)
    …mindset - Have familiarity with accelerator design , interconnects, DMAs, Memory sub- systems , CPU cores, SIMDs, debug and system level architectures - Have ... and Japan, and customers across all industries. Custom SoCs ( System on Chip ) live at the heart...the right trade-offs. Key job responsibilities As an ASIC Design Engineer , you will: * Develop and… more
    Amazon (06/14/25)
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  • Senior Design For Test Engineer

    Microsoft Corporation (Santa Clara, CA)
    …to CPU-based alternatives Microsoft DPU team in Santa Clara is looking for a Senior Design For Test Engineer to help develop their next generation complex SoCs ... experience. + 2+ years of industry experience as a Design For Test (DFT) engineer . + Hands...engineer . + Experience in designing and implementing In System Test structures + Experience with Synopsys tools for… more
    Microsoft Corporation (07/31/25)
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  • Design Engineer , Senior Director

    Applied Materials (Santa Clara, CA)
    …virtually every new chip and advanced display in the world. We design , build and service cutting-edge equipment that helps our customers manufacture display and ... of package designs. + Collaboration: Work closely with cross-functional teams, including chip designers, system engineers, and manufacturing teams, to ensure… more
    Applied Materials (08/07/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention ... product definitions, implements new innovative flows to improve our chip yield and to address multiple sectors, defines Reset...Tegra chips. The team is also handling the architecture, design , and synthesis of multiple System -level modules.… more
    NVIDIA (06/19/25)
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  • SoC RTL Security Design Engineer

    Google (Sunnyvale, CA)
    …cross-functional role, you will coordinate and co- design with our software and system hardware counterparts. The ML, Systems , & Cloud AI (MSCA) organization ... with 3 years of experience working on security design . + Experience interacting with software, system ...delivering unparalleled performance, efficiency, and integration. As a SoC Design Engineer , you will join a team… more
    Google (08/08/25)
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