- Qualcomm (Santa Clara, CA)
- …Group, Engineering Group > CPU Engineering **General Summary:** We are hiring a talented engineer for CPU System Debug Architecture/RTL engineer targeted for ... power devices. In this role, you will work with chip architects to conceive of the micro-architecture and help...in one or more of the following areas: CPU System Debug including ARM Debug Architecture, Micro-architecture Debug techniques… more
- TP-Link North America, Inc. (Irvine, CA)
- …+ Familiarity with embedded operating systems (eg, RTOS, Linux) and real-time system design . + Experience with hardware interfaces such as UART, SPI, I2C, ... About Us: Headquartered in the United States, TP-Link Systems Inc. is a global provider of reliable...are seeking a Junior Embedded System Software Engineer (Smart Home) to design , develop, and… more
- Siemens (Fremont, CA)
- …of technology and physics to deliver better products in the increasingly complex world of chip , board, and system design .We are seeking a passionate and ... Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around...highly skilled software engineer to join the Questa Visualizer Debug R&D team… more
- Meta (Sunnyvale, CA)
- …SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build...development 3. RTL development using Verilog, System Verilog and HLS 4. Soft and hard IP… more
- Broadcom (San Jose, CA)
- …communications algorithms or standards (802.3 Ethernet) to hardware and understanding of system design tradeoffs for high volume applications. Must have good ... design . You will involve in engineering implementation spec writing from marketing/ system requirements, RTL design and verification, synthesis, static timing… more
- Amazon (Cupertino, CA)
- …custom silicon solutions * Participate in various aspects of physical design : full chip floorplanning, circuit analysis, power/clock distribution, timing ... Annapurna Labs we are at the forefront of hardware co- design not just in Amazon Web Services (AWS) but...and healthy, and managing the full lifecycle of our systems at the huge scale and complexity of AWS.… more
- Google (Sunnyvale, CA)
- …of complex ASICs in advanced technology nodes at floorplan block, subsystem, and chip levels. + Oversee physical design of internal IPs and third-party ... related field, or equivalent practical experience. + 7 years of physical design experience with industry-standard tools, languages, and methodologies relevant to the… more
- Amazon (San Diego, CA)
- …to ensure functional correctness . Work with the design and communication systems team and participate in system level verification using test benches ... Kuiper's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites... systems - Familiarity with Matlab - Modem design verification experience - System C or… more
- NVIDIA (Santa Clara, CA)
- …Comprehensive Testing & OS Vetting: Develop and enhance automated frameworks for System -on- Chip (SOC) validation, including daily sanity and regression testing. ... We're looking for a versatile and highly motivated Software Engineer to join our team. In this role, you'll...automated test frameworks, writing comprehensive test suites, and performing system /OS validation. + Data Engineering / Systems … more
- Meta (Sunnyvale, CA)
- …netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications. **Required ... Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints for...the various partition blocks 2. Develop SOC Timing Full chip Flat & Hierarchical Constraints for Functional & DFT… more