• ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA, you'll join a group of ... BS (or equivalent experience) in Electrical Engineering or Computer Engineer or related degree required, advanced degrees (MS, PhD)...plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT , timing… more
    NVIDIA (08/28/25)
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  • Senior Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    …RTL, logic synthesis and verification, knowledge of Place and Route, and understanding of Design -for- test ( DFT ) is a plus. + Proficiency in scripting ... We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and...automated tools. + Create prototypes of patentable ideas on test chips and drive them to be deployed across… more
    NVIDIA (08/13/25)
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  • Sr. RTL Design Engineer - Wireless…

    Amazon (San Diego, CA)
    …underserved communities around the world. Come work at Amazon! We're hiring a Sr. RTL Design Engineer - Wireless Modem within a high performance ASIC design ... and meeting the power objectives . Create standalone verification test bench to verify the correctness of your block....C and DPI-C. . Ensure that the block meets DFT , timing and power targets by working closely with… more
    Amazon (10/03/25)
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  • Lead Application Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …activities associated with Cadence EDA tools for Synthesis, Logical Equivalency Checking (LEC), Design -for- Test ( DFT ), Place & Route and Static Timing ... on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job...in one or more of these areas: + Synthesis, DFT , Logical Equivalency Checking + Low Power Design more
    Cadence Design Systems, Inc. (07/18/25)
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  • ASIC Design Engineer , Cloud-Scale…

    Amazon (Cupertino, CA)
    …of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, ... and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring… more
    Amazon (09/19/25)
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  • Senior Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    …analysis of low power circuits, eg power gating, decaps, multi-vt is required. + Understanding of Design -for- test ( DFT ) and logic design is a plus. + ... you'll be doing: + Participate in cutting edge Processor design in deep submicron technologies. + Work as part...Work as part of a global circuits team to design the state of the art in silicon monitors… more
    NVIDIA (07/12/25)
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  • High Speed RTL Design Engineer

    Broadcom (San Jose, CA)
    …tools such as NCVerilog, NCSIM, Simvision, Lint.** + **Exposure to Design for test , understanding of scan concept and writing DFT friendly RTL.** + **Deep ... of experience in high speed ADC based SerDes RTL design .** + **Proficient with Verilog-HDL/System Verilog coding for PAM4...interconnect architectures such as 100G/200G per lane PAM4 and design trade-offs to drive attainment on metrics such as… more
    Broadcom (08/16/25)
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  • Senior ASIC Design Engineer

    Amazon (San Diego, CA)
    …right silicon solutions, and meeting the power objectives . Create standalone verification test bench to verify the correctness of your block . Work with the ... verification team and participate in System level verification using test benches constructed using UVM, System C and DPI-C...C and DPI-C . Ensure that the block meets DFT , timing and power targets by working closely with… more
    Amazon (07/09/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …balance between frequency and power/area/congestions/yield/etc. + Work on all aspects of DFT / Test timing such as timing constraints, timing analysis, timing ... as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology....technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If… more
    NVIDIA (09/09/25)
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  • Senior ASIC Synthesis Engineer

    NVIDIA (Santa Clara, CA)
    …area, congestion tradeoffs + Drive timing closure and power/area optimization across multiple design blocks + Work with DFT and Verification teams to ensure ... as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology....to stand out from the crowd: + Knowledge of DFT / Test logic including JTAG, scan, high speed… more
    NVIDIA (09/30/25)
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