- NVIDIA (Santa Clara, CA)
- …analysis of low power circuits, eg power gating, decaps, multi-vt is required. + Understanding of Design -for- test ( DFT ) and logic design is a plus. + ... you'll be doing: + Participate in cutting edge Processor design in deep submicron technologies. + Work as part...Work as part of a global circuits team to design the state of the art in silicon monitors… more
- Amazon (Cupertino, CA)
- …of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, ... and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ensuring… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …activities associated with Cadence EDA tools for Synthesis, Logical Equivalency Checking (LEC), Design -for- Test ( DFT ), Place & Route and Static Timing ... on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job...in one or more of these areas: + Synthesis, DFT , Logical Equivalency Checking + Low Power Design… more
- Broadcom (San Jose, CA)
- …tools such as NCVerilog, NCSIM, Simvision, Lint.** + **Exposure to Design for test , understanding of scan concept and writing DFT friendly RTL.** + **Deep ... of experience in high speed ADC based SerDes RTL design .** + **Proficient with Verilog-HDL/System Verilog coding for PAM4...interconnect architectures such as 100G/200G per lane PAM4 and design trade-offs to drive attainment on metrics such as… more
- Amazon (San Diego, CA)
- …right silicon solutions, and meeting the power objectives . Create standalone verification test bench to verify the correctness of your block . Work with the ... verification team and participate in System level verification using test benches constructed using UVM, System C and DPI-C...C and DPI-C . Ensure that the block meets DFT , timing and power targets by working closely with… more
- NVIDIA (Santa Clara, CA)
- …balance between frequency and power/area/congestions/yield/etc. + Work on all aspects of DFT / Test timing such as timing constraints, timing analysis, timing ... as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology....technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If… more
- NVIDIA (Santa Clara, CA)
- …area, congestion tradeoffs + Drive timing closure and power/area optimization across multiple design blocks + Work with DFT and Verification teams to ensure ... as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology....to stand out from the crowd: + Knowledge of DFT / Test logic including JTAG, scan, high speed… more
- NVIDIA (Santa Clara, CA)
- …to hear from you! What you'll be doing: + Support the deployment of advanced Design -For- Test ( DFT ) and Automatic Test Pattern Generation (ATPG) solutions ... We are now looking for a Senior ASIC Engineer in the area of DFX ATPG flows...degree in EE + 10+ years of experience in Design -For- Test + Strong understanding of ATPG tools… more
- General Atomics (Poway, CA)
- …initial release engineering drawings and revision changes for manufacturing readiness (DFM, DFT , DFQ, et al), coordinate with design engineering and others ... initial release engineering drawings and revision changes for manufacturing readiness (DFM, DFT , DFQ, et al), coordinate with design engineering and others… more
- Xylem (San Diego, CA)
- …product electrical and test -related issues.** **Develop, maintain, and enhance automated test programs using LabVIEW.** ** Design test fixtures and ... in new product introductions, ensuring a smooth transition from design to production, with focus on test ...layout.** **Exposure to statistical process control analysis.** **Understanding of DFT ( Design for Testability) and DFM (… more