• Sr Principal DFT Application…

    Cadence Design Systems, Inc. (Cary, NC)
    …We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate knowledge and experience in scan chain ... years of professional experience in SoC/ASIC Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT insertion… more
    Cadence Design Systems, Inc. (09/05/25)
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  • Senior Principal ASIC DFT Engineer

    Northrop Grumman (Morrisville, NC)
    …history. Northrop Grumman Mission Systems, Digital Technologies Group, is seeking an ASIC DFT Engineer to join our team of highly qualified, diverse individuals ... DoD Secret clearance.** **Roles and Responsibilities:** + Responsible for DFT ( Design for Testabilty) aspects of ASIC...+ Experience in full product life cycle of ASIC Design + Experience with Cadence and/or Mentor test… more
    Northrop Grumman (07/08/25)
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  • Principal Design Engineer

    Microsoft Corporation (Raleigh, NC)
    …LINT + CDC (Clock Domain Crossing) + DRC ( Design Rule Checking) + Develop basic test benches. + Support verification, DFT ( Design for Test ), and ... achieve that mission. We are looking for a **Principal Design Engineer ** to work in the dynamic...+ Analog mixed-signal designers + Verification engineers + Physical design and DFT teams + Other front-end… more
    Microsoft Corporation (09/30/25)
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  • Principal Design Engineer Manager…

    Microsoft Corporation (Raleigh, NC)
    …both architectural and micro-architectural intent. + Interface with physical design (PD), design for test ( DFT ), and other teams to optimize tradeoffs ... and optimize the Cloud infrastructure. We are looking for a **Principal Design Engineer Manager - AI Network Silicon** to join the team. Microsoft's mission… more
    Microsoft Corporation (09/26/25)
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  • Principal Digital Design Engineer

    Cadence Design Systems, Inc. (Cary, NC)
    … implementation + Embedded uC Designs + Synthesis and SDC Creation + Scripting of design automation + Debugging verification test cases / SVA's to cover the ... quality. The candidate will contribute to digital architecture, digital RTL, low power design , synthesis and timing analysis, and behavioral coding for all IPs in… more
    Cadence Design Systems, Inc. (09/11/25)
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  • Senior Principal ASIC Static Timing…

    Northrop Grumman (Morrisville, NC)
    …Electrical or Computer Engineering + Knowledge of Synthesis, Place & Route (P&R), and Design -for- Test ( DFT ) methodologies + Active DoD Secret Clearance or ... Systems, Digital Technologies Group, is seeking a Static Timing Engineer to join our team of highly qualified, diverse...propose changes to fix them + Work closely with design , verification, design -for- test and physical… more
    Northrop Grumman (07/11/25)
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