• ASIC Engineer, Design

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, network ... IP for data center applications. **Required Skills:** ASIC Engineer, Design Responsibilities: 1. Architecture exploration 2. Micro-architecture development 3. RTL… more
    Meta (08/01/25)
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  • Experienced or Senior Design Engineer…

    The Boeing Company (Seal Beach, CA)
    …in **Mechanical Flight Controls** to join our Out-of-Production (OoP) Mechanical (Mech) Systems Design Engineering (DE) team based in **Seal Beach, CA** . This role ... regulations. The ideal candidate will possess a deep understanding of design principles, aircraft performance, and regulatory requirements, ensuring that our… more
    The Boeing Company (10/05/25)
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  • Senior Physical Design Engineer

    NVIDIA (Santa Clara, CA)
    …to join our dynamic team today! We are actively looking for Physical design Engineers with RTL2GDS experience to implement complex high performance and low power ... and rolling in functional, Timing ECO's and netlist formal verification . + Physical verification - ERC, DRC, LVS...experience. + 6+ years of hands-on experience in Physical design . + Place and route tool experience with Synopsys… more
    NVIDIA (07/24/25)
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  • Senior Applications Engineer - DDR Design…

    Cadence Design Systems, Inc. (San Jose, CA)
    …an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San Jose, CAJob DescriptionThe Cadence IP team develops industry ... DDR4/5, LPDDR4/5/5X, HBM2/3, GDDR6* Perl/Python Scripts* Experience on memory subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, RTL … more
    Cadence Design Systems, Inc. (10/04/25)
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  • Nvidia 2026 Internships: Hardware ASIC…

    NVIDIA (Santa Clara, CA)
    …your resume, you're expressing interest in one of our 202 6 Hardware ASIC Design Internships. We'll review resumes on an ongoing basis, and a recruiter may reach ... areas could be required : + Digital Systems, Digital Design , VLSI Design , RTL Design...Power/Clock Distribution, Packaging, P&R and Timing Closure + Performance, Verification , and Emulation Methodology Depending on the internship role,… more
    NVIDIA (09/02/25)
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  • Staff Software Design Quality Engineer

    Stryker (San Jose, CA)
    **Stryker** is hiring a **Staff Software Quality Engineer, Design Assurance** to support our Medical's Digital Health division and portfolio Software as a Medical ... Device (SiMD) to execute on Digital Health projects as a software design quality assurance engineer for pre-market new product development projects. **Workplace… more
    Stryker (08/29/25)
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  • Senior Mask Design Engineer - Hardware

    NVIDIA (Santa Clara, CA)
    …is our life's work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer? If yes, We would love to hear from you! We are looking for a ... Senior Mask Layout Design Engineer, someone who is excited to join a...- particularly virtuoso. + Experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Primeyield.… more
    NVIDIA (08/28/25)
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  • MTS Circuit Design Engineer, HSIO

    Micron Technology, Inc. (Folsom, CA)
    …communicate and advance faster than ever. We are searching for a High Speed I/O Design engineer at our Micron Technology's HBM Team in Folsom, California. As a high ... speed Design engineer, you will be working for intensive applications...for Memory designs. + Excellent problem-solving skills in physical verification of custom layout. + Multiple Tape out support… more
    Micron Technology, Inc. (08/22/25)
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  • STA Engineer (eInfochips Inc)

    Arrow Electronics (San Jose, CA)
    …based on product specification, which includes, static timing analysis, IR/EM and physical verification through which design will be validated based on the ... product specification + Design and development of Chip implementation flow, place and...feedback, addition of flops, registers and memory etc. + Design the product internal standard cell placement and routing… more
    Arrow Electronics (08/29/25)
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  • Lead Applications Engineer - DDR Design IP

    Cadence Design Systems, Inc. (San Jose, CA)
    …teams, definers and designers . Write application notes, user guides, articles, design ideas, new product proposals, and evaluation kit manuscripts for internal ... Nice to have : . Experience on memory subsystem verification and/or performance analysis . Knowledge of System Verilog...performance analysis . Knowledge of System Verilog and FPGA design . Knowledge of AXI, DFI and MIPI protocols… more
    Cadence Design Systems, Inc. (10/04/25)
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