• Senior Mixed Signal Design Engineer

    NVIDIA (Santa Clara, CA)
    …join this diverse team and help move the needle! We are looking for a senior engineer to be part of the mixed-signal design team building next generation NVLINK. ... characterization. + Help by defining circuit requirements and complete design from schematic, layout, and verification to...and complete design from schematic, layout, and verification to characterization. + Conduct schematic design more
    NVIDIA (07/24/25)
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  • FPGA/ASIC Design Engineer (Silicon…

    SpaceX (Irvine, CA)
    FPGA/ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... ultimate goal of enabling human life on Mars. FPGA/ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...+ Participate in all phases of ASIC and/or FPGA design flow (eg synthesis, timing closure, verification )… more
    SpaceX (06/12/25)
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  • Digital Design Engineer

    Meta (San Diego, CA)
    **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital ... our industry leading virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block… more
    Meta (08/01/25)
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  • Hardware Design Engineer 5

    ManpowerGroup (Mountain View, CA)
    Our client, a leader in the technology sector, is seeking a Hardware Design Engineer 5 to join their team. As a Hardware Design Engineer 5, you will be ... will align successfully in the organization. **Job Title:** Hardware Design Engineer 5 **Location:** Austin, TX and...RTL design using SystemVerilog. + Experience in design verification and debugging, including RTL quality… more
    ManpowerGroup (06/24/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the ... requirements and system limitations, and deliver a fully verified design by working closely with verification engineers....fully verified design by working closely with verification engineers. + Deliver a synthesis/timing clean design more
    NVIDIA (07/31/25)
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  • Design Automation Engineer

    Broadcom (San Jose, CA)
    …already have a Candidate Account, please Sign-In before you apply.** **Job Description:** ** Design Automation Engineer ** This position is part of a team tasked ... checks into design cockpits + Regression testing of flows and verification checks + Parasitic extraction and simulation, abstract and LEF/DEF generation, LVS/ERC… more
    Broadcom (07/28/25)
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  • Principal Engineer , VLSI Design

    SanDisk (Milpitas, CA)
    …of digital design in NAND Flash memory, focusing on micro architecture, RTL design , verification , logic synthesis, and timing analysis to deliver a design ... of innovation. We are looking for an experienced Staff Engineer to lead and deliver projects for our Memory...and area goals. ESSENTIAL DUTIES AND RESPONSIBILITIES: + RTL design and verification in Verilog, RTL linting,… more
    SanDisk (07/17/25)
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  • Sr. Staff CPU Physical Design CAD…

    Qualcomm (Santa Clara, CA)
    …that push the envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer , you will build and support the world's best ... nodes (5nm or lower) + Solid understanding of digital design , timing analysis and physical verification +...of digital design , timing analysis and physical verification + Strong user of industry-standard place-and-route tools such… more
    Qualcomm (07/08/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of ... RTL and SOC designs + Collaborate with architects, ASIC designers, and verification engineers to design sophisticated system-level modules such as Floorsweep,… more
    NVIDIA (06/19/25)
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  • CPU Physical Design - Low Power Signoff…

    Qualcomm (San Diego, CA)
    …GDSII implementation. + Ability to collaborate and resolve issues wrt constraints validation, verification , STA, Physical design , etc. + Knowledge of low power ... smarter, connected future for all. As a Qualcomm CPU Engineer , you will lead innovative Central Processing Unit (CPU)..., you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries… more
    Qualcomm (06/05/25)
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