- Silvus Technologies (Irvine, CA)
- …a fulfilling career._ THE OPPORTUNITY Silvus is seeking a full-time **_Senior FPGA Design Engineer_** reporting to the _Director of FPGA Engineering_ on the _FPGA ... the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal… more
- Arrow Electronics (San Jose, CA)
- **Position:** Physical Design Engineer (Einfochips Inc) **Job Description:** **What candidate will Be Doing:** + Netlist to-GDSII implementation, including ... top-level floorplanning,, Design partitioning, Top level block to block/over the block...and top levels, addressing timing, congestion, IR-drop, and physical verification challenges. + Proficient with industry-standard tools: Synopsys ICC2,Fusion… more
- Amazon (Cupertino, CA)
- …and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and architectures, ... power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification , ECO and sign-off - Develop physical design methodologies… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Protium is leading product in FPGA Emulation/Prototyping domain. This role is to design , verification , timing closure and hardware validation of the FPGA IPs. ... gate array intellectual properties (FPGA IPs) for Protium platform, including design , verification , integration, timing closure, documentation and releasing the… more
- Micron Technology, Inc. (Folsom, CA)
- …communicate and advance faster than ever. We are searching for a High Speed I/O Design engineer at our Micron Technology's HBM Team in Folsom, California. As a ... high speed Design engineer , you will be working for...for Memory designs. + Excellent problem-solving skills in physical verification of custom layout. + Multiple Tape out support… more
- Amazon (San Diego, CA)
- …to unserved and underserved communities around the world. Role for Kuiper Sr. RFIC Layout design engineer : As a Sr. RFIC Layout design engineer , ... processes and product designs for analog circuits. * Proficiency in verification software for Design Rule Checks (DRCs) and Layout vs Schematic (LVS) are… more
- Northrop Grumman (Los Angeles, CA)
- …making history. Northrop Grumman Advanced Weapons has an opening for a FPGA Digital Design Engineer with an active clearance, to join our team of qualified, ... circuitry for digital electronic equipment and other hardware systems. Determines design approaches and parameters. Analyzes equipment to establish operating data,… more
- Google (Mountain View, CA)
- Senior CPU Physical Design Engineer , Silicon + _link_ Copy link + _email_ Email a friend _corporate_fare_ Google _place_ Austin, TX, USA; Mountain View, CA, USA ... practical experience. + 5 years of experience with physical design flow such as constraints, synthesis, floor planning, place...place and route, clock tree synthesis (CTS), or physical verification . + Experience in one or more sign-off convergence… more
- Google (Sunnyvale, CA)
- Physical Design Flow and Methodology Engineer + _link_ Copy link + _email_ Email a friend _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience ... innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific… more
- General Atomics (Poway, CA)
- …systems. We currently have an exciting opportunity for a seasoned Systems Engineer to define next generation communications modems and integrate them into ground ... new or existing systems on GA-ASI, Unmanned Air Systems (UAS). + Design communications systems and document their architecture by creating interconnect diagrams,… more
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