• Design Methodology Engineer

    Qualcomm (San Diego, CA)
    …Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** Qualcomm's Design Technology team is seeking a motivated engineer to drive ... methodologies in die-level IR drop, STA, and power. The engineer should be proficient in static timing analysis using...Engineering, or related field and 4+ years of ASIC design , verification , validation, integration, or related work… more
    Qualcomm (05/01/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This position ... . + Collaborate and coordinate with architects, other designers, pre- and post- silicon verification teams, synthesis, timing and back-end teams to accomplish… more
    NVIDIA (03/12/25)
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  • DFT Design Engineer , AWS Machine…

    Amazon (Cupertino, CA)
    … from micro-architecture through physical design - Good knowledge of design verification (DV) simulation methodologies - Experience with large gate-level ... Optimization Engineering Team you'll be responsible for the design and optimization of hardware in our data centers....cost effective DFT methodologies * Perform RTL coding and Verification * Participate in Silicon debug and… more
    Amazon (05/05/25)
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  • ASIC Design Engineer , Blink/Ring…

    Amazon (Sunnyvale, CA)
    …Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA - Work with pre- silicon verification teams to assist in defining test-plans/test-benches - Work with ... Description Join the team which delivers highly differentiated silicon into Blink and Ring battery powered devices. Our team works on state-of-the art SoCs in a… more
    Amazon (02/15/25)
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  • Senior Mixed Signal Design Engineer

    NVIDIA (Santa Clara, CA)
    …join this diverse team and help move the needle! We are looking for a senior engineer to be part of the mixed-signal design team building next generation NVLINK. ... silicon characterization. + Help by defining circuit requirements and complete design from schematic, layout, and verification to characterization. + Conduct… more
    NVIDIA (04/13/25)
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  • Senior Mixed Signal Design Engineer

    NVIDIA (Santa Clara, CA)
    …join this diverse team and help move the needle! We are looking for a senior engineer to be part of the mixed-signal design team building next generation NVLINK. ... silicon characterization. + Help by defining circuit requirements and complete design from schematic, layout, and verification to characterization. + Conduct… more
    NVIDIA (03/11/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the ... on features, performance requirements and system limitations, and deliver a fully verified design by working closely with verification engineers. + Deliver a… more
    NVIDIA (05/02/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …with architects, ASIC designers, and verification engineers to design sophisticated system-level modules such as Floorsweep, In- silicon measurement, ... We are now looking for a Senior ASIC Design Engineer to join our System...digital design concepts and experience in ASIC design flow including RTL design , verification… more
    NVIDIA (03/20/25)
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  • RTL Design Engineer , Hardware…

    Amazon (Sunnyvale, CA)
    …Fire TV and Amazon Echo. What will you help us create? The Role: As an RTL Design Engineer , you will be part of an advanced architecture team that is exploring ... for advanced functional blocks. You will participate in the design verification and bring-up of such blocks...bring-up of these blocks either in an FPGA or silicon by potentially writing test scripts, analyzing lab data,… more
    Amazon (04/30/25)
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  • Senior Physical Design Methodology…

    NVIDIA (Santa Clara, CA)
    …next generation of best-in-class products. Our teams focus is on architecture and design of CMOS and Silicon -Photonics high-speed chip interfaces (NVLink, IEEE, ... Floor planning, Clock and Power distribution, Place and Route, Integration and Verification . + Strong background with hierarchical design approach, top-down … more
    NVIDIA (04/19/25)
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