• DFT Engineer, Google Cloud

    Google (Sunnyvale, CA)
    DFT Engineer, Google Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and mentoring more junior team ... field, or equivalent practical experience. + 3 years of experience in DFT architecture, implementation, ATPG, and verification for SoCs. + Experience with… more
    Google (12/13/25)
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  • DFT Quality Engineer

    Broadcom (San Jose, CA)
    …have a Candidate Account, please Sign-In before you apply.** **Job Description:** ** DFT Quality Engineer** Broadcom's ASIC Product Division is seeking candidates for ... a DFT Quality Engineer position at our San Jose design...through Research & Development of comprehensive Design for Test ( DFT ) structures, patterns & test strategies. You will work… more
    Broadcom (12/12/25)
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  • HBM/DDR/SerDes DFT Verification Lead…

    Broadcom (San Jose, CA)
    …Jose, California Development Center. We are seeking a highly skilled HBM and SerDes DFT Verification Engineer to join our dynamic team. In this role, you will play ... our HBM, DDR and SerDes designs through comprehensive Design for Test ( DFT ) verification strategies. You will work collaboratively with cross-functional teams to… more
    Broadcom (12/06/25)
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  • SoC DFT Engineer, Google Cloud

    Google (Sunnyvale, CA)
    SoC DFT Engineer, Google Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and mentoring more junior ... field, or equivalent practical experience. + 5 years of experience in DFT architecture, implementation, and verification for SoCs. + Experience in silicon bring-up,… more
    Google (11/25/25)
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  • Staff DFT Engineer

    Broadcom (San Jose, CA)
    …**Job Description:** Broadcom's CSG division is seeking candidates for a Staff DFT engineer position. The successful candidate will be responsible for developing and ... DFx solutions while optimizing the cost for test. **Responsibilities** + Own IP DFT architecture, implementation, verification, signoff STA constraints for DFT +… more
    Broadcom (11/26/25)
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  • Senior DFT Static Timing Analysis Engineer,…

    Google (Sunnyvale, CA)
    Senior DFT Static Timing Analysis Engineer, Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... timing analysis and timing ECO creation, timing margins). + Experience in DFT architectures and associated test methodologies. + Experience in Tessent generated … more
    Google (12/05/25)
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  • DFT IC Design Engineer

    Broadcom (San Jose, CA)
    …please Sign-In before you apply.** **Job Description:** Broadcom is searching for a DFT IC Design Engineer to join the Data Center Solutions Group. This position ... this position will require in-depth knowledge and expertise towards DFT related aspects of IC Design through RTL and...are not limited to the following:** + Execution of DFT implementation, verification, and debug + Working with BISR,… more
    Broadcom (12/10/25)
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  • DFT Engineer

    Broadcom (San Jose, CA)
    …you apply.** **Job Description:** Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading most ... network switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, to implementation, verification, timing closure, ATE pattern bringup. .… more
    Broadcom (11/19/25)
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  • ASIC DFT DV Technical Leader

    Cisco (San Jose, CA)
    …**Your Impact:** You will be in the Silicon One development organization as a senior DFT verification lead in San Jose, CA. You will work with Front-end RTL teams, ... physical design teams to understand chip architecture and drive high-quality DFT verification. **Key Essential Functions:** + Responsible for thorough test planning… more
    Cisco (12/13/25)
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  • Senior Principal DFT Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …looking for SoC/ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate knowledge and experience in scan chain insertion, compression scan ... SoC/ASIC Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT...( DFT ) + Should possess intimate knowledge of DFT insertion flows + Basic scan chain insertion using… more
    Cadence Design Systems, Inc. (10/30/25)
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