• ASIC Engineer, DFT

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test ( DFT ) methodologies, implementation, and ... are looking for individuals with a background in Design for Testability ( DFT ) methodologies and implementation for IP/SOC, with demonstrated use and understanding of… more
    Meta (08/01/25)
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  • DFT Engineer (eInfochips)

    Arrow Electronics (Santa Clara, CA)
    **Position:** DFT Engineer (eInfochips) **Job Description:** **Position: DFT Engineer** **Location: San Jose CA (Remote)** **Experience: 8+ Years** **What You'll ... Be Doing:** Develop and implement comprehensive DFT architectures tailored to specific design requirements. Design and implement robust DFT infrastructure,… more
    Arrow Electronics (07/29/25)
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  • Lead ASIC DFT Engineer

    Google (Mountain View, CA)
    …related field, or equivalent practical experience. + 8 years of experience in DFT or physical design. + Experience with scan insertion, Automatic Test Pattern ... (JTAG), Internal JTAG (IJTAG) tools and flow. + Experience with DFT Electronic Design Automation (EDA) Tools like Tessent/Genus/FC/Simvision, etc. **Preferred… more
    Google (08/27/25)
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  • DFT Senior Manager

    Broadcom (San Jose, CA)
    …you apply.** **Job Description:** Broadcom's ASIC Product Division is seeking candidates for a DFT Manager position at our San Jose Design Center. As a DFT ... Manager, you will lead a group of highly performing DFT Engineers working on delivering high quality custom silicon...customers. The successful candidate will be responsible for leading DFT programs all the way from pre-sales through to… more
    Broadcom (08/20/25)
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  • DFT Design Engineer, AWS Machine Learning…

    Amazon (Cupertino, CA)
    …Key job responsibilities * Develop, implement and verify state-of-the-art Design for Test ( DFT ) architectures * Work with block designers to integrate DFT ... Work with physical design team to setup and implement DFT insertion flow * Develop high coverage and cost...insertion flow * Develop high coverage and cost effective DFT methodologies * Perform RTL coding and Verification *… more
    Amazon (08/04/25)
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  • Senior DFT Engineer

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. NVIDIA's DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan ... teams to drive scalable, automated solutions. + Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to...field + 5+ years of hands-on experience in Design-For-Test ( DFT ) + Deep knowledge of DFT tools,… more
    NVIDIA (06/17/25)
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  • Senior DFT Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …experience) with 5+, MSEE with 3+, or PhD with 2+ years of experience in DFT , system architecture, or RTL design. + Understanding of fundamental DFT topics, such ... Excellent understanding of MBIST and IOBIST fundamentals. + Experience in architecting DFT access mechanisms in 3D stacked and dielet/chiplet based designs, and UCIe… more
    NVIDIA (07/01/25)
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  • Senior DFx/RTL Engineer

    Cisco (San Jose, CA)
    …teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. **Key Responsibilities:** + Responsible ... for implementing the Hardware Design-for-Test ( DFT ) features that support ATE, in-system test, debug and...of the designs. + Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and… more
    Cisco (07/22/25)
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  • Display Finance Deputy CFO

    Applied Materials (Santa Clara, CA)
    …careers at Applied. **Position Summary:** Display and Flexible Technologies ( DFT ) leverages the materials engineering, deposition and inspection equipment expertise ... and monitor that are in use around the world. DFT is an externally reported segment that is part...looking for a versatile finance leader to partner with DFT executives to not only drive financial performance (profitable… more
    Applied Materials (08/07/25)
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  • Physical Design Engineer - Synthesis, PNR, STA

    SanDisk (Milpitas, CA)
    …to work whole digital SPR flow from RTL to GDS, include Synthesis, DFT scan insertion, PNR, STA timing analysis, IRdrop power analysis, DRC/LVS verification. ... PT, StarRC ESSENTIAL DUTIES AND RESPONSIBILITIES: + **Synthesis and DFT scan insertion** + Familiar timing constraint and qualify,...file in Synthesis. + Be able to timing and DFT analysis to improve Synthesis and DFT more
    SanDisk (08/08/25)
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