- Micron Technology, Inc. (Folsom, CA)
- …of I/O post-Silicon validation methodologies + In-depth knowledge of industry standard HSIO DFT architecture + 10+ years of experience in memory address and data ... path architecture/design + 5+ years of experience in system timing budgeting + Deep understanding of signal integrity, channel characteristics, and ESD design techniques and topologies. The US base salary range that Micron Technology estimates it could pay for… more
- NVIDIA (Santa Clara, CA)
- …and spec validation + Partner with other engineering groups including ASIC, DFT , ATE, silicon validation, fab process, software and quality teams to coordinate ... efforts and resolve silicon issues + Initiate and drive process improvements/preventative actions through root cause analysis + The ideal candidate will always look to improve workflows, products, functions and methodologies while working multi-functionally to… more
- Amazon (Cupertino, CA)
- …to improve physical design flows and methods * Collaborate with RTL, DFT designers to ensure high quality design implementation Basic Qualifications Bachelors' ... degree or higher in Electrical Engineering, Computer Engineering Graduation date between May 2023 and December 2025 Scripting internship/project experience with Python, Perl or equivalent Strong understanding of VLSI circuit design fundamentals Have taken at… more
- General Atomics (Poway, CA)
- …Indicator, Doppler, Pulse Doppler, Waveform, Interferometry, Phase Shift, CFAR, DFT , Multi-Static, DSP, Digital Signal Processing, Clutter Cancellation **Salary:** ... $98,100 - $171,398 **Travel Percentage Required** 0 - 25 **Relocation Assistance Provided** Provided **US Citizenship Required?** Yes **Clearance Required?** Desired **Clearance Level** Mid-Level (3-7 years) **Workstyle** Hybrid General Atomics is committed to… more
- Broadcom (Irvine, CA)
- …Understanding of memory behavioral and physical models is a plus + Understanding of DFT schemes and chip level integration is a plus + Familiarity with test setups, ... silicon testing and debug is a plus + Comfortable in running simulators, writing automation scripts, and are tools savvy + Good communication, interpersonal, and leadership skills + Motivated, self-driven and good at multi-tasking **Qualifications** Requires a… more
- NVIDIA (Santa Clara, CA)
- …Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with compute farm interaction: software deployment, performance ... optimization, containers, etc. NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're… more
- NVIDIA (Santa Clara, CA)
- …and random testing methodologies + Lead front-end design flows (Lint/CDC/Synthesis/ DFT /LEC/STA) and coordinate with back-end teams for successful chip tape-outs ... + Drive silicon bring-up efforts and performance optimization + Collaborate with multi-functional teams to align technology roadmaps with business objectives + Establish and maintain standard methodologies for mixed-signal design and verification What we need… more
- Amazon (San Diego, CA)
- …PHY/MAC bring-up. * Exposure to firmware-hardware interaction debugging. * Knowledge of DFT /DFD, scan chain, or BIST validation. * Familiarity with signal processing ... concepts and/or RF test automation. Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include:… more
- Amazon (San Diego, CA)
- …firmware on DUTs to reduce test time and increase self-testability. - Analog DfT and RF-BIST techniques. - Performing RF measurements such as load pull, ... s-parameters, noise parameters, IIP3, and automating equipment using Python and MATLAB. - RF test equipment such as network analyzers, spectrum analyzers, oscilloscopes, signal generators, and probe-stations. - High volume automated test of beamforming systems… more
- Arrow Electronics (San Jose, CA)
- …of design team who oversees **fullchip SDCs** and works with physical design and DFT teams to close **fullchip timing** in multiple timing modes. + Option to also ... do block level RTL design or block or top-level IP integration. + Helping develop efficient methodology to promote block level **SDCs to fullchip** , and to bring fullchip SDC changes back to block level. + Helping develop and apply methodology to ensure… more