• Senior Optical packaging design engineer

    Applied Materials (Santa Clara, CA)
    …Product Life Cycle (PLC) process by defining Design For Transportability ( DFT ) requirements and influencing product design. Identify and execute continuous ... engineering disciplines and operations personnel to develop solutions that adhere to DFT and DFM requirements. Successful Candidates For This Position Will Have MS… more
    Applied Materials (08/07/25)
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  • SOC Design - STA, Hardware Compute Group

    Amazon (Sunnyvale, CA)
    …signoff flow. * Work for Systems and Architecture, SoC Integration, Verification, DFT , Mixed Signal, IP owners, Synthesis, Place & Route and other local/remote ... defining architecture, micro-architecture, RTL design and functional verification. * Experience with DFT and DFM flows. * Must have good communication and analytical… more
    Amazon (08/01/25)
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  • ASIC Implementation Engineer - Synthesis

    Meta (Sunnyvale, CA)
    …5. Perform RTL Lint and work with the Designers to create waivers 6. Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults 7. Develop Timing ... Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks 8. Developing Automation scripts and Methodology for all FE-tools… more
    Meta (08/01/25)
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  • Senior ASIC Engineer - DFX

    NVIDIA (Santa Clara, CA)
    …you! What you'll be doing: + Support the deployment of advanced Design-For-Test ( DFT ) and Automatic Test Pattern Generation (ATPG) solutions + Work with multiple ... of ATPG tools Ways to stand out from the crowd: + Knowledge of DFT including fault models, ATPG, fault simulation, and diagnosis + Experience with Silicon testing… more
    NVIDIA (07/26/25)
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  • SOC RTL Design Engineer, Hardware Compute Group

    Amazon (Sunnyvale, CA)
    …Clocking, Reset, Test & Debug. - Develop and implement methodologies for I/O, DFT , Debug, Clocking and Power Management. Basic Qualifications - BS degree or higher ... tape outs of complex, high-volume SoCs in advanced design nodes - Experience with DFT tools for scan and BIST insertion - Experience with using AI tools tools… more
    Amazon (07/24/25)
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  • Sr. SoC Design - EM/IR, Hardware Compute Group

    Amazon (Sunnyvale, CA)
    …and get the right vectors for different types of analysis including functional, DFT and other scenarios for which power numbers are needed. Basic Qualifications * ... defining architecture, micro-architecture, RTL design and functional verification * Experience with DFT and DFM flows Amazon is an equal opportunity employer and… more
    Amazon (07/24/25)
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  • VLSI CAD Engineer, ECO Tools - New College Grad

    NVIDIA (Santa Clara, CA)
    …automation, including mapping, patch size minimization, reconfiguration of clocks, power, and DFT , as well as incremental timing and power optimization. A thorough ... equivalent experience. + Experience across VLSI, including exposure to synthesis, clocks, DFT , power distribution, timing, and place & route. + Proficiency in C++.… more
    NVIDIA (07/14/25)
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  • Senior Principal Test Engineer (Hardware-ICT)

    Palo Alto Networks (Santa Clara, CA)
    …for test coverage and serviceability with ICT and boundary scan + Drive DfT (Design for Testability) and test coverage analyses from early Prototype design stages ... manufacturing testing experience + Experience with electronics system design and DfT + Experience with ICT vendor management, performance management and resource… more
    Palo Alto Networks (07/05/25)
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  • Senior ASIC Synthesis Engineer

    NVIDIA (Santa Clara, CA)
    …timing closure and power/area optimization across multiple design blocks + Work with DFT and Verification teams to ensure functional and timing correctness What we ... LEC) and methodologies. Ways to stand out from the crowd: + Knowledge of DFT /Test logic including JTAG, scan, high speed I/O loopback, and memory BIST. + Have… more
    NVIDIA (07/01/25)
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  • Senior ASIC Physical Design and Timing Engineer

    NVIDIA (Santa Clara, CA)
    …such as CPUs, GPUs or Network processor implementation or SOCs. + Understanding of DFT logic and experience with DFT timing closure for various modes eg, ... scan shift and capture, transition faults, BIST, etc. + Knowledge of deep sub-micron technology and associated process variations effects, including modeling and converging considering process variations. + Experience in methodology and/or flow development as… more
    NVIDIA (06/30/25)
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