- NVIDIA (Santa Clara, CA)
- …such as CPUs, GPUs or Network processor implementation or SOCs. + Understanding of DFT logic and experience with DFT timing closure for various modes eg, ... scan shift and capture, transition faults, BIST, etc. + Knowledge of deep sub-micron technology and associated process variations effects, including modeling and converging considering process variations. + Experience in methodology and/or flow development as… more
- NVIDIA (Santa Clara, CA)
- …timing convergence, such as GPUs, CPUs, DPUs/Network processors, or SOCs + Understanding of DFT logic and experience with DFT timing closure for various modes ... eg, scan, BIST, etc. + Understanding and timing closure of digital logic/macros in AMS designs/IPs. + Experience in methodology and/or flow development as well as automation. NVIDIA is widely considered to be the leader of AI computing, and one of the… more
- General Atomics (Poway, CA)
- …initial release engineering drawings and revision changes for manufacturing readiness (DFM, DFT , DFQ, et al), coordinate with design engineering and others to ... initial release engineering drawings and revision changes for manufacturing readiness (DFM, DFT , DFQ, et al), coordinate with design engineering and others to… more
- NVIDIA (Santa Clara, CA)
- …automation, including mapping, patch size minimization, reconfiguration of clocks, power, and DFT , as well as incremental timing and power optimization. A thorough ... + 3+ years experience broadly across VLSI, including exposure to synthesis, clocks, DFT , power distribution, timing, and place & route. Previous experience as a… more
- CommScope, Inc. (Sunnyvale, CA)
- …impedance geometries. . Coordinate with and apply best practices for SI, PI, DFM, DFT , DFA, EMI and mechanicals with cross functional teams and factories. . General ... manufacturing and assembly processes. . Familiarity with design rules and tools of DFM, DFT and DFA. . Good communication skills and be able to work with… more
- Google (Sunnyvale, CA)
- …via reviews and dashboards; work closely with design engineering teams on DFT and to manage dependencies for test development. + Develop technical documentation ... used for product test strategies, test plans, and test processes. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex,… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …(STA) and power analysis (Tempus, Primetime, Voltus, PTPX) + Design-For-Test ( DFT ) and optimization within implementation flow (Tessent, Modus, Tetramax) + Design ... Constraints (Spyglass, Litmus) + Design closure and optimization for PPA, run-time + Low power-driven verification, UPF expertise (Conformal, Formality) + Experience with advanced FinFET process nodes + Coding expertise in TCL, Python + Debug, triage,… more
- Google (Sunnyvale, CA)
- …document debug process and findings. + Identify Design for Testing ( DFT ) opportunities, document, and collaborate with design engineering hardware/software for ... implementation prior to manufacturing builds. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin,… more
- Broadcom (San Jose, CA)
- …**Exposure to Design for test, understanding of scan concept and writing DFT friendly RTL.** + **Deep understanding of high-speed serial interconnect architectures ... such as 100G/200G per lane PAM4 and design trade-offs to drive attainment on metrics such as performance, power, and cost over the project lifetime.** + **Experience in synthesis, CDC, static timing analysis.** + **Exposure to SDF annotated simulations with… more
- Cisco (San Jose, CA)
- …a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes + Option to also do ... block level RTL design or block or top-level IP integration + Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level + Helping develop and apply methodology to ensure correctness and… more