• Chip Lead, Silicon

    Google (Mountain View, CA)
    …teams for high quality tape-outs. + Experience in working with verification, DFT , physical design and emulation teams. + Experience in supporting the Post ... Silicon testing and taking the chip to production. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by… more
    Google (08/08/25)
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  • ASIC Design Manager, TPU Compute

    Google (Sunnyvale, CA)
    …low-power design techniques. + Knowledge of ASIC Verification, Design For Testing ( DFT ), Synthesis, Static Timing Analysis (STA), or Physical Design. In this role, ... you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries,… more
    Google (08/08/25)
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  • Senior Mechanical Structure Engineer

    SAIC (San Bernardino, CA)
    …analysis including pressurized systems, modal analysis, discrete Fourier transform ( DFT ) frequency domain methods + Solid understanding of structural mechanics ... including non-linear stress/strain curves, fatigue and fracture analysis, corrosion mechanisms, thermal stress effects + Strong Experience with structural analysis (both closed form and using finite element tools) with static and dynamic loading + A basic… more
    SAIC (08/07/25)
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  • Digital Design Engineer, Reality Labs Silicon AI…

    Meta (Sunnyvale, CA)
    …design **Preferred Qualifications:** Preferred Qualifications: 13. Experience in DFT /Testability requirement definition and understanding of test program development ... 14. Python, or similar scripting experience 15. Familiarity with low-power design techniques 16. Experience using C for system verification 17. Master's degree in Electrical Engineering, Computer Engineering, relevant technical field, or equivalent practical… more
    Meta (08/01/25)
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  • SoC Physical Design Engineer

    Meta (Sunnyvale, CA)
    …(CTS), routing, static timing analysis and signoff 2. Collaborate with RTL design, DFT , verification, and power teams to ensure seamless integration and secure QOR ... 3. Optimize for power, performance, and area (PPA) using industry-standard tools and methodologies 4. Contribute to automation of physical design flows and improve design productivity **Minimum Qualifications:** Minimum Qualifications: 5. Currently has, or is… more
    Meta (08/01/25)
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  • Senior ASIC Design Engineer - Hardware

    NVIDIA (Santa Clara, CA)
    …deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams. + Get involved in end-to-end cycle of ASIC execution starting from ... micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup. What we need to see: + BS in Electrical Engineering or equivalent experience (MS preferred) + 3+ years of relevant work experience. + Deep understanding of… more
    NVIDIA (07/29/25)
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  • Coating Inspector - NACE Level III (CM Inspector…

    Atlas (Oakland, CA)
    …with project specs and DOT standards + Utilize tools such as DFT gauges, surface profile comparators, environmental monitors, and holiday detectors + Verify ... environmental conditions and ensure proper curing times and application procedures + Maintain accurate inspection records, daily logs, and photographic documentation + Coordinate with field crews, contractors, and engineering teams to ensure compliance +… more
    Atlas (07/29/25)
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  • ASIC Design Engineer

    Broadcom (San Jose, CA)
    …tool suite * Timing Analysis using Synopsys Primetime tool * Formal Verification * DFT concepts of Scan, BIST. * Strong Perl and Tcl scripting skill Other highly ... desirable experience: o 802.3 Ethernet or NIC experience. o Low power design skills o Layer 1 through Layer 4 experience The candidate must have good personal communication skills, team working spirit, hardworking, and motivated to be part of a highly… more
    Broadcom (07/26/25)
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  • Sr. Physical Design Methodology Engineer,…

    Amazon (Cupertino, CA)
    …physical design work. Interface directly with RTL, Physical Design, Package Design, DFT teams to improve methodologies and efficiencies. Be able to independently ... troubleshoot digital tool flow usage and deploy solutions; Fluent in scripting languages such as TCL, Python, etc. and able to build scalable and efficient flows to support parallel design developments Create Dashboard and Central reports for project tracking… more
    Amazon (07/26/25)
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  • CAD Flow Development Engineer

    NVIDIA (Santa Clara, CA)
    …checking. + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Familiarity with Machine Learning/Deep Learning NVIDIA is widely considered ... to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you. Your base… more
    NVIDIA (07/25/25)
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