- Cisco (San Jose, CA)
- Product Test Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1444752) + Location:San Jose, California, US + Area of InterestSupply Chain + Compensation ... in Silicon Operations, and with Cisco Systems NPI teams. Collaborate with DFT , Reliability, Quality, Failure Analysis and Manufacturing teams to resolve silicon… more
- Microsoft Corporation (Mountain View, CA)
- …to help achieve that mission. We are looking for a **Principal Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) ... (Design Rule Checking) + Develop basic test benches. + Support verification, DFT (Design for Test), and post-silicon validation activities in collaboration with… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job Overview: This Digital IC ... with Cadence EDA tools for Synthesis, Logical Equivalency Checking (LEC), Design-for-Test ( DFT ), Place & Route and Static Timing Analysis (STA).You may get involved… more
- NVIDIA (Santa Clara, CA)
- …methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are problem solver and ... frequency and power/area/congestions/yield/etc. + Work on all aspects of DFT /Test timing such as timing constraints, timing analysis, timing...to stand out from the crowd: + Experience with DFT timing closure for various modes eg scan shift,… more
- CommScope, Inc. (Sunnyvale, CA)
- Principal PCB Design Engineer Req ID: 79088 Location: Sunnyvale, California, United States, 94089 In our 'always on' world, we believe it's essential to have a ... world:** The RUCKUS Hardware Team is seeking an experienced engineer with expertise in high-speed, mixed-signal PCB layout design...with and apply best practices for SI, PI, DFM, DFT , DFA, EMI and mechanicals with cross functional teams… more
- ManpowerGroup (Santa Clara, CA)
- Our client, a leader in the technology industry, is seeking a RTL Design Engineer to join their team. As a RTL Design Engineer , you will be part of the design ... align successfully in the organization. **Job Title:** RTL Design Engineer **Location:** Santa Clara, CA (Onsite 3 days per...I/O SoC in 3 nm processes. + Implement SOC DFT features (TAP controller, GPIOs, ESD structures, etc.) into… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical Synthesis using advanced ... with the Designers to create waivers 6. Perform RTL DFT Analysis and improve the DFT coverage...of experience as a Front End Synthesis & Integration Engineer 12. Experience with RTL Synthesis and design optimization… more
- NVIDIA (Santa Clara, CA)
- …on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you are problem solver and ... You'll Be doing: + As a Front-End ASIC Synthesis Engineer , you will own RTL synthesis and gate level...power/area optimization across multiple design blocks + Work with DFT and Verification teams to ensure functional and timing… more
- NVIDIA (Santa Clara, CA)
- …lines many thousands of times per day. We are seeking a CAD R&D Engineer excited to innovate in algorithms related to ECO automation, including mapping, patch size ... minimization, reconfiguration of clocks, power, and DFT , as well as incremental timing and power optimization....place & route. Previous experience as a physical design engineer would be ideal. + Proficiency in C++ +… more
- SanDisk (Milpitas, CA)
- …where you'll be at the center of innovation. We are looking for an experienced Engineer to lead and deliver projects for our Memory Design team. This is a great ... RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT , timing analysis and closure + Balance design trade-offs with modularity,… more