- Applied Materials (Santa Clara, CA)
- …Product Life Cycle (PLC) process by defining Design For Transportability ( DFT ) requirements and influencing product design. Identify and execute continuous ... Materials and its Supply Base. Provide advanced training and support to Packaging Engineer III. Performs other duties as assigned. Duties will vary according to the… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Engineer in the area of DFX ATPG flows and methodologies. Do you like to think creatively and enjoy solving challenges that ... be doing: + Support the deployment of advanced Design-For-Test ( DFT ) and Automatic Test Pattern Generation (ATPG) solutions +...to stand out from the crowd: + Knowledge of DFT including fault models, ATPG, fault simulation, and diagnosis… more
- NVIDIA (Santa Clara, CA)
- …lines many thousands of times per day. We are seeking a CAD R&D Engineer excited to innovate in algorithms related to ECO automation, including mapping, patch size ... minimization, reconfiguration of clocks, power, and DFT , as well as incremental timing and power optimization....+ Experience across VLSI, including exposure to synthesis, clocks, DFT , power distribution, timing, and place & route. +… more
- Palo Alto Networks (Santa Clara, CA)
- …capabilities to build our next-generation network firewalls. As a senior test engineer , you will be responsible for building advanced test platforms for network ... for test coverage and serviceability with ICT and boundary scan + Drive DfT (Design for Testability) and test coverage analyses from early Prototype design stages… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... GPUs or Network processor implementation or SOCs. + Understanding of DFT logic and experience with DFT timing closure for various modes eg, scan shift and… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... such as GPUs, CPUs, DPUs/Network processors, or SOCs + Understanding of DFT logic and experience with DFT timing closure for various modes eg, scan, BIST, etc. +… more
- Amazon (Sunnyvale, CA)
- …Clocking, Reset, Test & Debug. - Develop and implement methodologies for I/O, DFT , Debug, Clocking and Power Management. Basic Qualifications - BS degree or higher ... tape outs of complex, high-volume SoCs in advanced design nodes - Experience with DFT tools for scan and BIST insertion - Experience with using AI tools tools… more
- General Atomics (Poway, CA)
- …initial release engineering drawings and revision changes for manufacturing readiness (DFM, DFT , DFQ, et al), coordinate with design engineering and others to ... initial release engineering drawings and revision changes for manufacturing readiness (DFM, DFT , DFQ, et al), coordinate with design engineering and others to… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- Cisco (San Jose, CA)
- ASIC Design Engineer - Design & Timing Constraints Apply (https://jobs.cisco.com/jobs/Login?projectId=1439367) + Location:San Jose, California, US + Area of ... leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products,...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing… more