• Senior RF ATE Engineer , Amazon Leo Silicon…

    Amazon (San Diego, CA)
    …communities around the world. Come work at Amazon! As Senior RF ATE Engineer , you will engage with an experienced cross-disciplinary staff to conceive and design ... lots. - Develop and transfer to volume production RF and high-speed digital die probing techniques to improve accuracy of identifying good dice and improve yield.… more
    Amazon (12/05/25)
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  • Senior Timing Methodology Engineer , Custom…

    NVIDIA (Santa Clara, CA)
    …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... of precision, craftsmanship, and artistry required to make billions of transistors function on every die at technology nodes as deep as 5 nm and beyond, this is an… more
    NVIDIA (11/20/25)
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  • Senior Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... of precision, craftsmanship, and artistry required to make billions of transistors function on every die at technology nodes as deep as 5 nm and beyond, this is an… more
    NVIDIA (11/20/25)
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  • Senior Circuit Design Engineer - Power…

    NVIDIA (Santa Clara, CA)
    …wave of computing. We are now looking for a motivated Senior Circuit Design Engineer in Power Modeling and Simulation to join our dynamic and growing Circuits ... of abstraction and complexity. + Model and simulate power delivery networks (PDN) from die level all the way to platform level. + Perform detailed block-level and… more
    NVIDIA (11/18/25)
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  • Yield and Integration Engineer

    Teledyne (Goleta, CA)
    …equipment_ + _Infrared Imaging_ + _Hermetic packaging (solder, seam seal, wirebond, WLP, die attach, leak testing, etc.)_ Required: + BS in engineering or a science, ... MS preferred + 2+ years as a Process, Design, Quality or Manufacturing Engineer + Ability to work in cleanroom environment. **_Applicants must be either a US… more
    Teledyne (11/14/25)
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  • Signoff Methodology Engineer - New College…

    NVIDIA (Santa Clara, CA)
    …inventiveness and intelligence. We are seeking an innovative Timing Methodology Engineer to help drive multi-physics sign-off strategies for the world's leading ... of precision, craftsmanship, and artistry required to make billions of transistors function on every die at technology nodes as deep as 5 nm and beyond, this is an… more
    NVIDIA (11/05/25)
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  • Hardware Development Engineer , AWS CQC…

    Amazon (Pasadena, CA)
    …Computing in Pasadena, CA, is looking to hire a Hardware Development Engineer with experience in semiconductor process development - and in particular wirebonding, ... tools, wire bonding tools, saw dicing, stealth dicing, electrical probing on wafer/ die Preferred Qualifications - 4+ years of industry or academic research… more
    Amazon (11/04/25)
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  • SMTS Design Engineer , NVEG

    Micron Technology, Inc. (San Jose, CA)
    …to the development of memory products that are best-in-class in terms of die size, performance, reliability, and power. Our NVEG organization is dedicated to ... memory products. **Position Overview** The Senior Member of Technical Staff Design Engineer in Micron's NVEG organization contributes to the development of new… more
    Micron Technology, Inc. (10/25/25)
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  • R&D IC Design Engineer

    Broadcom (Irvine, CA)
    …for design validation Perform design tradeoff analysis - leakage, dynamic power, die size, schedule, resource, priority, etc. silicon bring up and validation, ATE ... program bring up **Job Requirement:** BS degree in EE or computer Engineering. Minimum of 8 years of work experience with direct related technical skill MS degree/Ph.D in EE or Computer Engineering with 6 years of work experience. Good knowledge of ARM… more
    Broadcom (12/30/25)
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  • R&D IC Design Engineer

    Broadcom (Irvine, CA)
    …design validation + Perform design tradeoff analysis - leakage, dynamic power, die size, schedule, resource, priority, etc. + silicon bring up **Job Requirement:** ... + _B.S degree in EE or computer Engineering. Minimum of 12 years of work experience with direct related technical skill_ + _M.S degree/Ph.D in EE or Computer Engineering with 10 years of work experience._ + Good knowledge of ARM subsystem + Good knowledge of… more
    Broadcom (12/30/25)
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