• Senior Mechanical Engineer

    Cisco (San Jose, CA)
    …or related degree with 7+ years of relevant experience *Experience with Aluminum Die -cast and sheet metal design *Prior experience with CAD tools such as (Creo, ... SolidWorks, NX) *Experience with thermal lab testing and CFD modeling tools *Experience with leading complex product design programs **Preferred Qualifications** *Master of Science in Mechanical Engineering or related degree with 4+ years of relevant… more
    Cisco (12/13/25)
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  • IC Power, IR and EM Sr. Application…

    Cadence Design Systems, Inc. (San Jose, CA)
    …to IR/EM sign-off. + Fundamental understanding of interconnect modeling, package analysis, and die modeling. + Ability to write and debug automation code in Python ... or Tcl. + Solid grasp on foundational algorithms to solve numerical and graph problems. + Basic idea on how EDA and Semiconductor industry eco-system works. + Alacrity to be an excellent team player. The annual salary range for California is $84,000 to… more
    Cadence Design Systems, Inc. (11/15/25)
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  • Chip Power Integrity Engineer

    Broadcom (San Jose, CA)
    …integrity problems for a variety of products including 2.5D, spanning from small die with high impedance challenges to massively large chips with large power ... consumption and significant step load challenges + You have also been involved with helping customers solve voltage budget constraints at the system level through PDN simulations **More specifically we are looking for a chip power integrity expert with the… more
    Broadcom (11/06/25)
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  • ASIC Engineering Technical Leader

    Cisco (San Jose, CA)
    …Team** You will be part of the Silicon One development organization as an ASIC implementation engineer in San Jose, CA. As a member of this team you will be involved ... DFT & test strategy aspects for new silicon device models, bare die & stacked die , driving re-usable test and debug methodologies and standards. + Work with… more
    Cisco (11/12/25)
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  • Materials Manager

    NVIDIA (Santa Clara, CA)
    …and test hardware, outlining complete BOM configurations to ensure all wafer-level, die , substrate, and packaging materials are properly defined. + Set up product ... our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.… more
    NVIDIA (12/19/25)
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  • IC / Semiconductor Package Designer

    Broadcom (Irvine, CA)
    …Designer** **Role Overview** We are seeking an experienced IC Packaging Engineer to drive next-generation package architecture, design, and productization using ... teams (224G/112G SerDes, PCIe Gen 6/7, ADC/DAC, etc.) to optimize chip floorplan, die bump patterns, and IO architecture for advanced node products. + Co-optimize… more
    Broadcom (12/02/25)
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