- Meta (Sunnyvale, CA)
- …the entire stack, through algorithms to architecture, transistors to firmware. As a Design Verification Engineer at Meta's Reality Labs, you will work with a ... multiple state of the art machine learning IPs. **Required Skills:** Design Verification Engineer - Machine Learning Accelerators Responsibilities: 1. Work with… more
- Meta (Sunnyvale, CA)
- …entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with a ... for multiple state of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers and architects defining … more
- Meta (Sunnyvale, CA)
- …the entire stack, from transistor, through architecture, to firmware, and algorithms.As a Design Verification Engineer at Meta Reality Labs, you will work with a ... test cases for multiple state of the art IPs. **Required Skills:** Design Verification Engineer (University Grad) Responsibilities: 1. Work with researchers and… more
- Meta (San Diego, CA)
- …the entire stack, from transistor, through architecture, to firmware, and algorithms.As a Design Verification Engineer at Meta Reality Labs, you will work with a ... cases for multiple state of the art IPs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers and architects defining… more
- Jet Propulsion Laboratory (Pasadena, CA)
- …Gate Array (FPGA) Verification Engineer IV** , responsible for the verification of the digital subsystems for spaceborne and airborne Radar Systems. The ... Management Team** and the Group Supervisor of the **Radar Digital Electronics Group** . We are seeking a **Field...RTAX. **What You Will Do** + Provide a robust verification and validation environment for FPGA-based control and signal… more
- Google (Sunnyvale, CA)
- …on TPU architecture and its integration within AI/ML-driven systems. As an ASIC Design Verification Engineer , you will be part of a team developing ASICs used ... innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific… more
- Qualcomm (Santa Clara, CA)
- …connected future for all. The team is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support. The ... responsibility of the position involves comprehensive pre-silicon test planning for digital power IP's, its testbench development using the advanced verification … more
- Siemens (Fremont, CA)
- …This Applications Engineer (AE) position delivers technical expertise for Functional Verification of digital , mixed-signal, and analog IC chip designs based ... Verification planning, Testbench development using SV/UVM methodologies, Functional verification and modeling of digital /mixed-signal ASICs and SoCs, Failure… more
- Qualcomm (Santa Clara, CA)
- …the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, ... responsibility of the position involves comprehensive pre-silicon test planning for digital power IP's, its testbench development using the advanced verification… more
- Palo Alto Networks (Santa Clara, CA)
- …to create an environment where we all win with precision. **Your Career** As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in ... starts and ends with our mission: Being the cybersecurity partner of choice, protecting our digital way of life. Our vision is a world where each day is safer and… more