• Senior Hardware Engineer - Micro-Architect

    quadric.io, Inc (Burlingame, CA)
    …a machine learning graph, the Quadric GPNPU executes both NN graph code and conventional C++ DSP and control code. Role: This is a rare opportunity to get in on the ... Power, Performance & Area (PPA) optimization + Contribute to timing closure through full product cycle (front end, back-end, tapeout) Requirements: + BS/MS or Ph.D.… more
    quadric.io, Inc (06/09/25)
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  • Sr Staff R&D Engineer

    The Walt Disney Company (Nicasio, CA)
    …flow-based models, variational autoencoders, and neural vocoders, optimized for professional soundtrack production. + Own end-to-end model lifecycle management: ... + Guide the development of personalized model adaptation workflows to support per-user tuning, cross-project continuity, and flexible deployment. + Collaborate with… more
    The Walt Disney Company (08/21/25)
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  • Senior ASIC Design Engineer, Project Kuiper

    Amazon (San Diego, CA)
    …wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. In this role you will: ... and cost constraints . Drive high quality designs for first- time right silicon solutions, and meeting the power objectives...laws and Company policies. Criminal history may have a direct , adverse, and negative relationship with some of the… more
    Amazon (07/09/25)
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  • Senior ASIC Verification Engineer

    Tarana Wireless (Milpitas, CA)
    …Sight connections. What you'll be doing: + Work with some of the best DSP , system, and software engineers to define verification strategies and execute plans at ... system or full chip level + Build and continuously improve verification...including: Medical, dental and vision benefits, 401K match, flexible time off and stock option. Join Tarana and help… more
    Tarana Wireless (06/26/25)
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