• Temporary Principal Packaging Engineer

    Unilever (San Francisco, CA)
    THE ROLE: TEMPORARY PRINCIPAL PACKAGING ENGINEER We are looking for a passionate and highly collaborative Principal Packaging Engineer Contractor to lead ... in the United States without sponsorship. CONTRACT LENGTH: Mid-November 2025 - Mid-May 2026 ( 6 Months) ​ The pay range for this position is $80-100 per hour… more
    Unilever (08/19/25)
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  • Principal Engineer , R&D

    Terumo Neuro (Aliso Viejo, CA)
    **12964BR** **Title:** Principal Engineer , R&D **Job Description:** Support and lead teams in the development of medical device products, including writing or ... medical devices. 5. Ability to read and prepare technical documentation. 6 . Possess working knowledge of standard machine shop equipment/processes and medical… more
    Terumo Neuro (08/19/25)
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  • Sr. Staff UI/Frontend Engineer (NetSec)

    Palo Alto Networks (Santa Clara, CA)
    …where we all win with precision. **Your Career** As a Software UI/Frontend Engineer of the Netsec UI team, you will collaborate with the product managers, ... team's most complex technical challenges. **Your Impact** As a Sr. Staff UI/Frontend Engineer , you will be instrumental in shaping how our customers understand and… more
    Palo Alto Networks (08/19/25)
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  • Senior Line Engineer

    United Airlines (Los Angeles, CA)
    …based on the needs of the operation. Work Schedule: 7.00pm PST- 6 .30am PST **Qualifications** What's needed to succeed (Minimum Qualifications): + Bachelor's degree ... technical field or equivalent relative work experience + Senior Line Engineer I: 5-8 years + Senior Line Engineer II: 8 years + Ability to interpret complex and… more
    United Airlines (08/19/25)
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  • Space Systems Engineer

    SAIC (El Segundo, CA)
    …SAIC is seeking a highly experienced **Sr. Principal** **S** **pace Systems Engineer ** to support Space Systems Command Space Domain Awareness and Combat Power ... program risks assessments and provides actionable recommendations to the chief engineer and program manager. + Independently collaborate with Government program… more
    SAIC (08/19/25)
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  • Union Stationary Engineer

    CBRE (Mountain View, CA)
    Union Stationary Engineer Job ID 225680 Posted 18-Aug-2025 Service line GWS Segment Role type Full-time Areas of Interest Engineering/Maintenance Location(s) ... geographies. **About the Role:** As a CBRE Union Stationary Engineer , you will be responsible for working, repairing, providing...holiday pay, and more! + Internal advancement available after 6 month mark + 40-45 hours a week +… more
    CBRE (08/19/25)
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  • Software Engineer , Language - Wearables

    Meta (Menlo Park, CA)
    …shipping products at the intersection of hardware, software and content.As a Language Software Engineer on the Reality Labs team at Meta, you can help build new, ... the web. We are hiring in multiple locations. **Required Skills:** Software Engineer , Language - Wearables Responsibilities: 1. Apply relevant AI and machine… more
    Meta (08/19/25)
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  • Temporary Packaging Engineer

    Unilever (San Francisco, CA)
    THE ROLE: TEMPORARY PACKAGING ENGINEER ​ We are looking for a Packaging Engineer (Contractor) to support our base business packaging projects. This part-time ... work in the United States without sponsorship. CONTRACT LENGTH: Mid-October 2025 - Mid-April 2026 ( 6 Months) ​ ​ The pay range for this position is $45-55 per hour… more
    Unilever (08/19/25)
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  • Manufacturing engineer

    LEMO Group (Rohnert Park, CA)
    Manufacturing engineer Rohnert Park, California USA * Permanent contract * As soon as possible Summary Translate customer requirements into cost effective designs ... as PEEK, POM, PTFE, FEP, VMQ, Rubber, Polyamide, Polyurethane, PA6. 6 , PPSU, PSU, etc. + Proficient CAD Drafting skills...and the use of natural resources. By helping to engineer , design, build, set up, distribute or sell our… more
    LEMO Group (08/18/25)
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  • Senior FPGA Design Engineer

    Silvus Technologies (Irvine, CA)
    …Science degree in Electrical Engineering, Computer Science, or relevant fields. + Minimum 6 years of demonstrated experience in FPGA design; 4 years of FPGA design ... experience with a Master's of Science degree; 2 years of FPGA design experience with a PhD degree. + Demonstrated experience with fixed point binary arithmetic and digital signal processing designs. + Proven expertise working with multiple clock-domain,… more
    Silvus Technologies (08/18/25)
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