• ASIC Design Engineer , Platform IP, Silicon

    Google (Mountain View, CA)
    …field, or equivalent practical experience. + 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or ... SystemVerilog. + Experience with logic synthesis techniques to improve RTL code, performance and...Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's… more
    Google (04/10/25)
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  • Physical Design Engineer , TPU

    Google (Sunnyvale, CA)
    …to the development of silicon-based ICs and chips. + Experience in logic synthesis, PnR, timing closure, and static timing analysis. Preferred qualifications: + ... be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's...design of internal IPs and third-party IPs, including digital logic , I/Os, analog PHYs, etc. + Setup and/or review… more
    Google (04/02/25)
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  • Senior Electrical Engineer (Automation)

    Kelly Services (El Dorado Hills, CA)
    **Job Summary:** We are seeking a Senior Electrical Engineer responsible for the electrical design, development, and testing of factory automation systems. Your role ... industrial components and machinery into automation systems, including designing custom circuitry and cabling. + Experience designing PLC-based control systems.… more
    Kelly Services (05/01/25)
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  • Post-Silicon SoC Validation & Emulation…

    Qualcomm (San Diego, CA)
    …help create a smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital and/or analog), optimize, verify, validate, ... products. * Assists in the creation of architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements. *… more
    Qualcomm (04/26/25)
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  • ASIC Engineer , Physical Design

    Meta (Sunnyvale, CA)
    …(SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical design implementation ... of multi-hierarchy low-power and high-performance designs, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing… more
    Meta (04/22/25)
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  • Staff Foundry PDK Enablement Engineer - HBM…

    Micron Technology, Inc. (Folsom, CA)
    …multiple DRAM chips on a high-speed memory controller with an integrated logic chip in one package, significantly increasing memory density and bandwidth through ... are seeking a highly skilled and motivated **PDK Enablement Engineer ** to join our team!. The ideal candidate will...for design teams on PDK usage and updates. + Custom flow evaluation for PDK health evaluation. + Participate… more
    Micron Technology, Inc. (04/19/25)
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  • Staff Foundry Technology Reliability…

    Micron Technology, Inc. (Folsom, CA)
    …multiple DRAM chips on a high-speed memory controller with an integrated logic chip in one package, significantly increasing memory density and bandwidth through ... are seeking a motivated and experienced Si Foundry Interface Engineer to focus on the reliability assessment of new...TMI_Aging simulations (Pass1& Pass2) to evaluate design degradation for custom and digital flow. + Analyze simulation results to… more
    Micron Technology, Inc. (04/19/25)
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  • Staff Foundry PDK Enablement Engineer

    Micron Technology, Inc. (Folsom, CA)
    …multiple DRAM chips on a high-speed memory controller with an integrated logic chip in one package, significantly increasing memory density and bandwidth through ... in the industry. We are hiring Foundry PDK Enablement Engineer ! You will be responsible for overseeing and driving...PDKs through rigorous testing and quality assurance processes. + Custom flow evaluation for PDK health evaluation. + Participate… more
    Micron Technology, Inc. (04/19/25)
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  • Sr. Staff IC CAD Engineer

    Power Integrations (San Jose, CA)
    …and power density. We are seeking a highly motivated Sr. Staff CAD Engineer to join our dynamic engineering team in capitalizing on this market transformation. ... Cadence schematic entry, mixed mode circuit simulation, layout design, layout verification, logic synthesis, place & route, SKILL code development and developing … more
    Power Integrations (04/16/25)
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  • Senior Mixed Signal Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now hiring for a Senior Mixed-signal Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the ... PCIE, USB) preferred + Have a deep understanding of Verilog or SystemVerilog, logic design and circuit modeling for mixed-signal blocks + Deep understanding of… more
    NVIDIA (04/13/25)
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