• ASIC Silicon Infrastructure Engineer

    Meta (Sunnyvale, CA)
    …ASIC design solutions, including but not limited to Source Control Management, Continuous integration , data management and reporting 3 . Manage the internal EDA ... **Summary:** META is hiring ASIC Silicon Infrastructure Engineer within our Reality Lab ASIC organization. We...EDA flow, CAD/automation and ASIC infrastructure to build efficient System on Chip (SoC) and IP for our AR/MR… more
    Meta (05/02/25)
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  • Programmer/Analyst (Research Software…

    Cedars-Sinai (Los Angeles, CA)
    …culturally and ethnically multifaceted community we serve. The Programmer/Analyst (Research Software Engineer ) is a key contributor to the AIM Program research team. ... design, complex algorithmic coding, and systematic approaches to application integration . The Programmer/Analyst works on new and existing applications, performs… more
    Cedars-Sinai (04/26/25)
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  • Quality Assurance Engineer

    Eliassen Group (Sacramento, CA)
    …testing activities across the entire software development lifecycle, including integration , system , performance, regression, user acceptance, disaster recovery, ... **Quality Assurance Engineer ** **Anywhere** **Type:** Contract **Category:** Quality Assurance (QA)...assurance or testing role supporting enterprise computing platforms and system development efforts + Minimum of TWO (2) years… more
    Eliassen Group (04/18/25)
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  • Design Verification Engineer (eInfochips…

    Arrow Electronics (Sunnyvale, CA)
    … Engineer (eInfochips Inc) **Job Description:** **Role: Design Verification Engineer ** **Location: Sunnyvale CA (Hybrid 3 days onsite)** **Experience: ... **Job Description:** **What candidate will Be Doing:** + At-least 8+ years of experience in System Verilog HVL and C++/C + At-least 8+ year of experience in UVM. +… more
    Arrow Electronics (03/12/25)
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  • Design Verification Engineer

    Qualcomm (San Diego, CA)
    …work experience. OR Master's degree in Science, Engineering, or related field and 3 + years of ASIC design, verification, validation, integration , or related work ... team is responsible for the complete design verification lifecycle, from system -level concept to tape out and post-silicon support. **Responsibilities:** + Define… more
    Qualcomm (04/19/25)
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  • Chemical Engineer

    Belcan (Livermore, CA)
    Chemical Engineer Job Number: 357303 Category: Chemical Description: Job Title: Chemical Engineer Pay Rate: $60.00-$65.00/hr DoE Location: ​​Livermore​, CA Zip ... determine composition of the produced fuel stream * Development of filtration systems to remove impurities from base methanol precursors. * Furthering the filtration… more
    Belcan (05/09/25)
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  • Staff Software Engineer

    Intuit (Mountain View, CA)
    …Experimentation, and Personalization) Product Development Team" as a "Staff Software Engineer " to build innovative solutions that help our customers succeed. As ... web applications and services. + Proven expertise as a full-stack engineer , proficient in both front-end and back-end technologies, capable of designing… more
    Intuit (05/03/25)
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  • Security Engineer - IR Threat Intelligence

    Meta (Sacramento, CA)
    …tooling and systems used by the team. **Required Skills:** Security Engineer - IR Threat Intelligence Responsibilities: 1. Track threat clusters posing threats ... **Summary:** Meta Security is looking for a Security Engineer - IR Threat Intelligence with extensive experience...the tooling of threat cluster tracking and intelligence data integration to existing systems . 5. Engage constructively… more
    Meta (03/19/25)
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  • Senior ASIC Design Verification Engineer

    NVIDIA (Santa Clara, CA)
    …discussions on architecture, intent, and implementation of the various IPs. + Enable system level integration by working with partner teams for test development ... sub- system level verification or MS preferred in Electrical, Computer Engineering with 3 + years' experience in unit level or sub- system level verification. +… more
    NVIDIA (03/06/25)
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  • ASIC Engineer , Design

    Meta (Menlo Park, CA)
    … Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture development. 3 . RTL development using Verilog, System Verilog and HLS. ... 4. Soft and hard IP identification, selection and integration . Collaboration with verification and emulation teams in test plan development and debug. 5.… more
    Meta (04/09/25)
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