• Package Design Engineer

    NVIDIA (Santa Clara, CA)
    …to incorporate various requirements in package designs + Work with off-shore fab and package assembly manufacturing partners to develop and implement package design ... rules What we need to see: + BS in EE or ME (or equivalent experience) + 3+ years package design experience + Strong programming skills (Perl, Python, Tcl desired) + Working knowledge of Cadence Allegro Packaging Design (APD) + Experience in 2.5D packages +… more
    NVIDIA (08/02/25)
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  • Bill of Materials (BoM) Manager

    Adecco US, Inc. (Vallejo, CA)
    …submittals, producing the engineering BoM from the Revit model, finalizing the fab drawings relative to the HCD set, addressing production floor requests, and ... reviewing the final BoM after project completion to improve the BoM process. + Perform additional assignments as required by the needs of the company or as directed by executives. + Work and collaborate with Team Members throughout the company for specific… more
    Adecco US, Inc. (08/02/25)
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  • Director, Technical Project/Program Management…

    Applied Materials (Santa Clara, CA)
    …defect knowledge base. - Collaborate with customer-facing engineers to understand fab defect troubleshooting methodologies, requirements, and high value problems by ... equipment types. - Interface and coordinate with business unit senior management to define program objectives and provide status updates. Develop product roadmap. - Develop and report program metrics. - Build defect case study collateral. Oversee company-wide… more
    Applied Materials (07/31/25)
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  • Process Development Engineer

    Teledyne (Goleta, CA)
    …development team, the successful candidate will have responsibility for engineering wafer fab processes including DUV lithography using ASML 5500, plasma etch, thin ... film deposition, and wet cleans for next generation infrared detector designs. Candidate will design and implement new processes and automate or improve existing ones to support aggressive technology development goals. Candidate will process and/or direct… more
    Teledyne (07/22/25)
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  • Ethernet NIC Software and Validation Engineer

    Broadcom (Irvine, CA)
    …to provide extensive system level ASIC test coverage prior to first silicon fab . Our software-based test harnesses are combined with extensive, deeply detailed test ... matrices to generate millions of system level test vectors. These harnesses execute on state of the art SMP servers, under production operating systems and software stacks, to provide a broad level of system level ASIC test coverage that complements… more
    Broadcom (07/21/25)
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  • EDA Infrastructure Engineer

    University of Southern California (Los Angeles, CA)
    …Electronics and Microdevices Superhub (California DREAMS) will promote innovation and lab-to- fab transition for RF and other technologies in the Southern California ... region. MOSIS 2.0 will play a critical role in providing access to university nanofabs and industry prototyping and production fabs in support of rapid prototyping for Government- and Industry-funded R&D projects. The primary end uses for the service span from… more
    University of Southern California (07/19/25)
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  • Test System Design Engineer 4 (ATS Irvine)

    Astronics (Irvine, CA)
    …Interference (EMI) requirements. + Must be able to read and understand assembly drawings, FAB drawings, indented BOMs and parts lists. + Good knowledge of metals and ... alloys and their properties and sheet metal design + 7+ years of hands on engineering design experience **Computer Skills:** + LabVIEW, Test Stand, LabWindows CVI, C/C++, VisualBasic, or C#. + Word processing, Spreadsheets, Internet software, E-mail, Database… more
    Astronics (07/18/25)
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  • Senior Reliability Engineer

    NVIDIA (Santa Clara, CA)
    …reports and presentations. What we need to see: + Firm technical background in wafer fab , and Flip Chip BGA and COWOS packaging technologies. + You are equipped with ... knowledge of CMOS devices physics, and familiar with reliability statistics, and models. + Familiar with industry standards (like JEDEC, IPC, AEC-Q100) + Proficient in reliability data analysis tool such as JMP, Weibull++ and/or Minitab + 8+ years of… more
    NVIDIA (07/17/25)
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  • Principal design engineer, VLSI Design Engineering

    SanDisk (Milpitas, CA)
    …We are building a cutting edge 3D memory in our multiple billion dollars Fab . Our memory provides performance, power, and endurance at a lower cost but on ... quality. The Memory Technology organization is a strategic entity for the company, and we are growing. Our group functions as a start-up within Sandisk, and offers a creative, fast paced, entrepreneurial work environment where you'll be at the center of… more
    SanDisk (07/17/25)
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  • Principal Engineer, VLSI Design Engineering

    SanDisk (Milpitas, CA)
    …We are building a cutting edge 3D memory in our multi-billion dollars Fab . Our memory provides performance, power, and endurance at a lower cost without ... forgoing quality. The Memory Technology organization is a strategic entity for the company and we are constantly growing. Our group functions as a start-up within Sandisk, and offers a creative, fast paced, entrepreneurial work environment where you'll be at… more
    SanDisk (07/17/25)
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