- Google (Mountain View, CA)
- …JAX, TensorFlow, PyTorch or similar. + Experience or interest in hardware verification technologies, formal methods, theorem proving, and hardware testing ... automating chip design: hardware-software co-design for ML models, hardware generation and verification , RTL optimization, and system design. + Engage and work in a… more
- Amazon (Sunnyvale, CA)
- …block and Sub System level. - Drive block physical implementation through synthesis, formal verification , floor planning, bus / pin planning, place and route, ... Mentor Graphics, Synopsys, or Others) to block design for synthesis, formal verification , floor planning, bus / pin planning, place and route, power/clock… more
- Qualcomm (San Diego, CA)
- …timing fixes and functional ECOs, debugging and fixing physical violations, and formal verification . The individual also should have deep knowledge on ... Fusion Compiler - Timing closure experience in Synopsys PTSI - Formal verification experience - Power domain analysis experience - Physical verification… more
- Meta (Sunnyvale, CA)
- …Experience in one or more of the following areas along with functional verification -SV Assertions, Formal , Emulation 12. Experience in EDA tools and scripting ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are...with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The… more
- Meta (Menlo Park, CA)
- …16. Experience in one or more of the following areas along with functional verification - SV Assertions, Formal , Emulation 17. Experience with verification ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are...closure. Along with traditional simulation, use other approaches like Formal and Emulation to achieve a bug-free design. The… more
- Meta (Sunnyvale, CA)
- …13. Experience in one or more of the following areas along with functional verification - SV Assertions, Formal , Emulation 14. Experience in development of UVM ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are...with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The… more
- Meta (Sunnyvale, CA)
- …11. Experience in one or more of the following areas along with functional verification - SV Assertions, Formal , Emulation 12. Experience in EDA tools and ... from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with an industry-leading… more
- Meta (Sunnyvale, CA)
- …Experience in one or more of the following areas along with functional verification - SystemVerilog Assertions, Formal , Emulation 12. Experience in Electronic ... the entire stack, through algorithms to architecture, transistors to firmware.As a Design Verification Engineer at Meta's Reality Labs, you will work with a group of… more
- Amazon (Sunnyvale, CA)
- …methodology - Develop, regress and deploy digital implementation flows including Synthesis and Formal Verification - Enable digital design teams to meet PPA ... methodology and debugging techniques - Familiar with basic Synthesis and Formal Verification methodology and flow development experience Preferred Qualifications… more
- Amazon (Cupertino, CA)
- …tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification , floor planning, bus / pin planning, place and ... power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification , ECO and sign-off - Develop physical design methodologies -… more