- Meta (Sunnyvale, CA)
- …Experience in one or more of the following areas along with functional verification -SV Assertions, Formal , Emulation 12. Experience in EDA tools and scripting ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are...with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The… more
- Meta (Sunnyvale, CA)
- …Experience in one or more of the following areas along with functional verification -SV Assertions, Formal , Emulation 12. Experience in EDA tools and scripting ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are...with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The… more
- Capgemini (Santa Clara, CA)
- …(Python, TCL). + Strong grasp of **functional coverage** , simulation, emulation, and formal verification . + Proven ability to **lead teams** , **influence ... **Architect and Implement Solutions** Design and deploy **end-to-end SoC verification environments** leveraging UVM, UPF, and advanced methodologies. **Engineer… more
- NVIDIA (Santa Clara, CA)
- …Strong proficiency in micro-architecture and RTL development using Verilog. + Experience with formal verification using JasperGold is a plus. + Deep expertise in ... on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most… more
- Amazon (Cupertino, CA)
- …tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification , floor planning, bus / pin planning, place and ... power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification , ECO and sign-off - Develop physical design methodologies -… more
- SpaceX (Sunnyvale, CA)
- …of design blocks using Verilog/SystemVerilog + Familiar with UPF (unified power format), formal verification , and DRC rule checking experience + Ability to work ... RTL and physical design Scan Design Rule Check (DRC) tools + Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems + Running and… more
- Palo Alto Networks (Santa Clara, CA)
- … formal methods, and silicon bring-up. + **Collaborate** with verification engineers to debug complex scenarios, close coverage, and add design-for-debug ... with DDR5 memory, Ethernet (IEEE 802.3), or search-algorithm accelerators. + Formal - verification ownership. + Hands-on silicon validation and lab bring-up.… more
- Actalent (Anaheim, CA)
- …for the Integration & Testing (I&T) of maritime programs. This role involves formal verification , formal validation, and system integration. Additional ... + Conduct integration and testing of maritime programs. + Perform formal verification and validation processes. + Support the creation of architectural drawings… more
- NVIDIA (Santa Clara, CA)
- …based SOCs + Prior hands-on experience in Ada/SPARK programming (including specification and formal verification ) and TLA+ formal verification modeling ... strong C and/or Ada/SPARK programming skills, and experience with formal methods, we want to hear from you! Join...revolutionizing the industry. We are making extensive use of formal methods to automate our work flow and increase… more
- Amazon (Hawthorne, CA)
- …-Master's or Ph.D degree in Electrical / Communications Engineering -Exposure to Formal verification -Experience with physical implementation flows Amazon is an ... time to revenue. Innovators will be delighted with our integrated verification /validation environment that is used to perform architectural modeling to post-silicon… more