- Cisco (San Jose, CA)
- …concepts + Scripting experience (Python, Perl, TCL, shell programming) + Experience with formal verification tools + Experience with emulation **Why Cisco?** At ... + Help define, evolve, and support our design methodology. + Collaborate with the verification team to address design bugs and close code coverage. + Work closely… more
- Transdev (Atwater, CA)
- …Experience with system engineering principles such as defining requirements and formal verification and validation methods + Test scripting ... Decompose system requirements and consequently design test plans and verification strategies that give Waymo the necessary evidence to...service + Improve the quality and coverage of the verification of a system + Build new processes that… more
- Qualcomm (San Diego, CA)
- …**Principal Duties and responsibilities:** + Complete ownership on Conformal Low Power and Formal Verification signoff for hier and flat CPU Subsytem on latest ... implementation. + Ability to collaborate and resolve issues wrt constraints validation, verification , STA, Physical design, etc. + Knowledge of low power flow (power… more
- NVIDIA (Santa Clara, CA)
- …and negative testing + Experience developing for safety critical platforms + Experience with formal verification + Passion for your work Your base salary will be ... to stand out from the crowd: + Experience with threat modeling, formal design analysis, hardware/firmware architecture, and other demonstrable security experience in… more
- Northrop Grumman (San Diego, CA)
- …constraints and achieving timing closure. + Generation of Test benches and support of formal VHDL Verification . + Experience with board RO system level debug ... organization. Experience with growing discipline organizations of Digital VHDL Design and Verification engineers is highly desired for this role. This Manager of… more
- Meta (Sunnyvale, CA)
- …NOC, Memory and Peripheral Subsystems 9. Experience with Synthesis, Timing Closure and Formal Verification Methodology 10. Master's or PhD degree in Electrical ... 3. Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug 4.… more
- Meta (Sunnyvale, CA)
- …NOC, Memory and Peripheral Subsystems 13. Experience with Synthesis, Timing Closure and Formal Verification Methodology 14. Master's or PhD degree in Electrical ... Soft and hard IP identification, selection and integration 5. Collaboration with verification and emulation teams in test plan development and debug 6. Collaboration… more
- NVIDIA (Santa Clara, CA)
- …+ Debugging timing violations and rolling in functional, Timing ECO's and netlist formal verification . + Physical verification - ERC, DRC, LVS etc. ... What we need to see: + Bachelor's or a Master's degree in Engineering or equivalent experience. + 6+ years of hands-on experience in Physical design. + Place and route tool experience with Synopsys ICC2 or Candence Innovus + Static timing analysis with… more
- Imperative Care (Campbell, CA)
- …test methods and associated fixturing/automation to support both explorative, characterization, and formal verification testing of the Company's products. + Your ... comparing performance of devices for concept selection, design optimization, and design verification in close collaboration with the preclinical and design groups. +… more
- Broadcom (San Jose, CA)
- …+ Collaborate with physical design team on constraint generation, timing closure analysis, formal verification , low power checks using UPF/CPF flows and ECO ... and resolve Lint and Clock/Reset Domain crossing issues in the design + Collaborate with verification team on test plan development, debugging, and coverage closure… more