- Cisco (San Jose, CA)
- …Cadence). + Experience with Spyglass CDC and glitch analysis. + Experience using Formal Verification : Synopsys Formality and Cadence LEC. + Experience with ... scripting languages such as Python, Perl, or TCL. . **Why Cisco?** At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that… more
- Microsoft Corporation (Mountain View, CA)
- …Synthesis, Placement, CTS and custom clocking, Routing, Static Timing, Physical Verification , Formal Equivalency, Power Efficiency, IR-Drop, and EM. You ... sign off blocks, subsystem/Subchip in the areas of static timing, physical verification , logics equivalence, low power verification and electromigration and IR… more
- Meta (Sunnyvale, CA)
- …through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement verification ... plans, and build test benches for block, IP, sub-system, and SoC level verification 2. Develop functional tests based on verification test plan 3. Drive Design … more
- Meta (Sunnyvale, CA)
- …transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement IP/SoC ... verification plans, build verification test benches to enable IP/sub-system/SoC level ...or more of the following areas: SystemVerilog Assertions (SVA), Formal , and Emulation 15. Prior working knowledge of Audio/image/Video… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... Verification to build IP and System On Chip (SoC)...traditional simulation, you will be using other approaches like Formal and Emulation to achieve a bug-free design. The… more
- Google (Sunnyvale, CA)
- ASIC Design Verification Engineer, University Graduate _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Early** Experience completing work as directed, and ... using SystemVerilog for ASICs. + Experience in power aware verification , gate level simulations, and post silicon bring-up. +...or formally verify designs with SVA and industry leading formal tools. + Identify and write all types of… more
- Butler America (Buena Park, CA)
- …experience in Python programming + Ability to identify, track, and resolve verification process/environment/artifact issues in a formal configuration and change ... Title : Sr. Software Verification Engineer Job ID#: 71737 Duration: Permanent Location:...on education and experience) Job Summary The Sr. Software Verification Engineer will design, develop, document, test and verify… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position offers ... silicon correlation. + Own the unit and sub-system level verification of various IPs, create functional test plans, and...as VCS-XA or equivalent tools, Gate Level Simulation or Formal Equivalence domains. + Proficiency in scripting language, such… more
- Amazon (Cupertino, CA)
- …ASIC physical design, and methodologies including synthesis, place and route, STA, IR, formal and physical verification . - Demonstrated level of expertise in PD ... job responsibilities Define, develop and deploy innovative physical design and verification methodologies (RTL2GDS) for ML Accelerator chips in advanced nodes Drive… more
- Northrop Grumman (Los Angeles, CA)
- …Experience in Test script development with HW interfaces + Experience performing formal requirements decomposition and/or verification + Works under only general ... and remediate software issues to support subsystem and system level Design Verification Tests (DVTs). + Communicate SW project status to the Software IPT… more