• ASIC Design Engineer - Design & Timing Constraints

    Cisco (San Jose, CA)
    …Cadence) + Experience with Spyglass CDC and glitch analysis + Experience using Formal Verification : Synopsys Formality and Cadence LEC. + Experience with ... scripting languages such as Python, Perl, or TCL **Why Cisco?** At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that… more
    Cisco (06/25/25)
    - Related Jobs
  • Design Implementation Engineer- Graphics

    Qualcomm (San Diego, CA)
    …detailed issues + Be Familiar with The latest EDA tools for synthesis, formal verification , timing analysis and physical design **Minimum Qualifications:** * ... Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR Master's degree in Computer Engineering,… more
    Qualcomm (06/21/25)
    - Related Jobs
  • ASIC Methodology/CAD Engineer, Silicon and Systems…

    Amazon (Sunnyvale, CA)
    …development in a production setting - Experience with UVM - Familiarity with formal verification techniques - Familiarity with the TCL programming language - ... Familiarity with bash scripting (or other shell) - Experience with HTML and basic web page development - Basic Linux administration experience - Strong written and verbal skills Amazon is an equal opportunity employer and does not discriminate on the basis of… more
    Amazon (06/11/25)
    - Related Jobs
  • Principal Product Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …flow, preferably on Genus and Innovus + Experience in Logic Design and Synthesis, Formal Verification , Low Power design, Physical Design and Timing Closure for ... block level and top level designs + Automation skills using Perl, Tcl and shell scripting essential + Knowledge of HDL - Verilog or System Verilog is preferred + Bonus to have logic design and/or timing closure skills + Strong analysis skills required to debug… more
    Cadence Design Systems, Inc. (06/10/25)
    - Related Jobs
  • Senior/Staff Digital Electrical Engineer - FPGA…

    Philips (San Diego, CA)
    …to established development procedures. + Leading the creation and execution of formal verification and validation plans in collaboration with Quality and ... Regulatory teams, actively participating in transferring designs from R&D to manufacturing and conducting technical design reviews with project teams and independent experts. **You're the right fit if:** + You've acquired 5+ years of experience in the design… more
    Philips (06/08/25)
    - Related Jobs
  • SDC Engineer (eInfochips Inc)

    Arrow Electronics (San Jose, CA)
    …Cadence) + Experience with Spyglass CDC and glitch analysis + Experience using Formal Verification : Synopsys Formality and Cadence LEC. + Experience with ... scripting languages such as Python, Perl, or TCL **What's In It for You:** At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That's why we offer competitive financial compensation, including various… more
    Arrow Electronics (06/06/25)
    - Related Jobs
  • Physical Design Methodology Engineer, Annapurna…

    Amazon (Cupertino, CA)
    …physical design flows, and methodologies including synthesis, place and route, STA, formal verification . - Proven track record of delivering metric driven ... PPA flow development and support. Preferred Qualifications - Demonstrated level of expertise in PD tools such as Innovus, ICC2, FusionCompiler, STA, and Sign-Off. - Experience in evaluating multiple vendor solutions and driving tool decisions. - Experience in… more
    Amazon (06/03/25)
    - Related Jobs
  • Senior Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …+ Conduct synthesis, linting, Clock Domain Crossing (CDC) analysis, and Formal Equivalence Verification (FEV). + Support System-on-Chip (SoC) integration ... various subsystems. + Collaborate with cross-functional teams, including architecture, verification , and physical design, to ensure designs meet specifications and… more
    Microsoft Corporation (08/08/25)
    - Related Jobs
  • Senior Software Engineer - C/C++, Qt, design…

    Siemens (Fremont, CA)
    …stacks like AWS, Azure, Google cloud etc. Exposure to Simulation or Formal -based Verification methodologies. Knowledge of Python, ML based techniques and ... algorithms Education A Bachelor's or Master's degree in Computer Science, Electrical Engineering, Electronics Engineering, or a related technical field from an accredited institution. Why us? Working at Siemens Software means flexibility - Choosing between… more
    Siemens (08/08/25)
    - Related Jobs
  • Staff Digital Design Engineer

    Northrop Grumman (San Diego, CA)
    …as oscilloscopes and logic analyzers. + Generation of Test Benches and support of formal VHDL Verification + Active/Current DoD Secret Clearance or higher level ... MSSDEAS Salary Range: $181,400.00 - $272,200.00 The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the… more
    Northrop Grumman (07/18/25)
    - Related Jobs