• ASIC Engineer , Formal…

    Meta (Austin, TX)
    **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... to build IP and System On Chip (SoC) for data center applications. As a Formal Verification Engineer , you will be part of a team working with the best in… more
    Meta (09/23/25)
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  • ASIC Engineer , Network Design…

    Meta (Austin, TX)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... Chip (SoC) for data center applications. As a Design Verification Engineer , you will be part of...or more of the following areas along with functional verification -SV Assertions, Formal , Emulation 11. Experience in… more
    Meta (09/30/25)
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  • ASIC Engineer , Design Verification

    Meta (Austin, TX)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of...or more of the following areas along with functional verification - SV Assertions, Formal , Emulation 14.… more
    Meta (09/23/25)
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  • ASIC Engineer , Design Verification

    Meta (Austin, TX)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... Chip (SoC) for data center applications. As a Design Verification Engineer , you will be part of...or more of the following areas along with functional verification -SV Assertions, Formal , Emulation 12. Experience in… more
    Meta (09/23/25)
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  • ASIC Engineer , Design Verification

    Meta (Austin, TX)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of...traditional simulation, you will be using other approaches like Formal and Emulation to achieve a bug-free design. The… more
    Meta (09/04/25)
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  • Senior Design Verification Engineer

    Microsoft Corporation (Austin, TX)
    …and optimize the Cloud infrastructure. We are looking for a **Senior Design Verification Engineer ** to join the team. **Responsibilities** + Perform pre-silicon ... as Python or Perl + Hands-on experience in Formal property verification , formal verification of computational data path designs Silicon Engineering IC4 -… more
    Microsoft Corporation (09/26/25)
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  • Design Verification Engineer

    Arrow Electronics (Austin, TX)
    **Position:** Design Verification Engineer **Job Description:** Principal Accountabilities * Responsible for architecting Verification Environment for ASIC ... and technical specification documents * Implement and maintain integrated end-to-end formal verification flow for the formal verification objective.… more
    Arrow Electronics (09/25/25)
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  • Principal Verification Engineer

    Microsoft Corporation (Austin, TX)
    …verification environments in industry standard languages like SVTB UVM or formal verification . **Other** **Requirements** **:** Ability to meet Microsoft, ... manage and optimize the Cloud infrastructure. We are looking for a **Principal** ** Verification ** ** Engineer ** to join the team. **Responsibilities** + Lead an… more
    Microsoft Corporation (09/26/25)
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  • Senior Verification Engineer

    Microsoft Corporation (Austin, TX)
    …manage and optimize the Cloud infrastructure. We are looking for a **Senior Verification Engineer ** to join the team. **Responsibilities** + Establish yourself ... verification environments in industry standard languages like SVTB UVM or formal verification . **Other Requirements:** Ability to meet Microsoft, customer… more
    Microsoft Corporation (09/25/25)
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  • Sr. ASIC Design Verification…

    Amazon (Austin, TX)
    …. Participate in the validation of ASIC implementations in Verilog/SystemVerilog . Run formal verification of complex blocks to ensure functional correctness . ... Matlab model : development or DV integration experience - Familiarity with formal verification techniques - Strong written and verbal skills Amazon is an equal… more
    Amazon (09/13/25)
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