- Cisco (San Jose, CA)
- …Cadence) + Experience with Spyglass CDC and glitch analysis + Experience using Formal Verification : Synopsys Formality and Cadence LEC. + Experience with ... ASIC Design Engineer - Design & Timing Constraints Apply (https://jobs.cisco.com/jobs/Login?projectId=1439367)...for this position reflects the projected hiring range for new hire, full-time salaries in US and/or Canada locations,… more
- NVIDIA (Santa Clara, CA)
- …innovative CAD tools and the latest process technologies. + Work on functional verification , perform CDC checks and formal equivalence. + Support post-si bringup ... NVIDIA is looking for an ASIC Design Engineer to join our Global Circuits Team! In...a "learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only… more
- Imperative Care (Campbell, CA)
- …test methods and associated fixturing/automation to support both explorative, characterization, and formal verification testing of the Company's products. + Your ... Job Title: Senior R&D Test Engineer Location : This position is based in...of devices for concept selection, design optimization, and design verification in close collaboration with the preclinical and design… more
- Elkay (Paso Robles, CA)
- …to thrive. From formal training to on-the-job development and exposure to new businesses, when you join Zurn Elkay, you will join a collaborative organization ... Senior Design Engineer **_The Company_** Zurn Elkay Water Solutions Corporation...with a variety of engineering initiatives that focus on New Product Development (NPD), VAVE, and continuous improvement of… more
- Lockheed Martin (Palmdale, CA)
- …tomorrow with you\. **Who You Are:** You are a detail\-oriented and results\-driven engineer with a strong background in systems engineering and test planning\. You ... or closely\-related engineering discipline . Experience with requirements definition, tracking and/or verification . Must be a US Citizen, must have a minimum final… more
- Amazon (Cupertino, CA)
- …of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ... TAT improvements Work with EDA tool vendors to evaluate new methods, resolve bugs, improve usability. Fine tune cloud...and methodologies including synthesis, place and route, STA, IR, formal and physical verification . - Demonstrated level… more
- NVIDIA (Santa Clara, CA)
- …a lasting impact on the world. We are looking for a motivated CAD Methodology Engineer to join our dynamic and growing team. If you like solving challenging problems ... in asynchronous digital design and verification in a highly multi-functional work environment then join...and provide test cases to EDA vendors. + Invent new methodologies to improve coverage and user efficiency by… more
- Microsoft Corporation (Mountain View, CA)
- …+ Conduct synthesis, linting, Clock Domain Crossing (CDC) analysis, and Formal Equivalence Verification (FEV). + Support System-on-Chip (SoC) integration ... to help achieve that mission. We are looking for a **Senior** **Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC)… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …flow, preferably on Genus and Innovus + Experience in Logic Design and Synthesis, Formal Verification , Low Power design, Physical Design and Timing Closure for ... on the world of technology. This opportunity is for an engagement focused Product Engineer (PE) in the Digital and Signoff Group (DSG) at Cadence. The Cadence DSG… more
- Leidos (Vista, CA)
- …**Leidos' Security Enterprise Solutions (SES)** operation is seeking a **Systems Test Engineer ** in **Vista, CA** to join our cross-functional engineering team using ... and people at checkpoints around the world. The **Systems Test Engineer ** will collaborate with Engineering, Project Management, Manufacturing, Training, Field… more