• Senior SRAM Engineer , Circuit Design

    NVIDIA (Santa Clara, CA)
    …using various flows and methodologies including: Static Timing analysis, EM and IR analysis, Formal Verification At NVIDIA, we have been at the forefront of ... We are now looking for a Senior SRAM Engineer ! The Full Custom Macro team at NVIDIA...a "learning machine," constantly evolving and adapting to seize new opportunities. We seek challenges that are not only… more
    NVIDIA (01/02/26)
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  • Engineer Software - Embedded and Real Time…

    Northrop Grumman (San Diego, CA)
    …to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have ... making history. Northrop Grumman Aeronautics Systems has an opening for a **Software Engineer - Embedded and Real Time** to join our team of qualified, diverse… more
    Northrop Grumman (12/18/25)
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  • Design Implementation Engineer

    Broadcom (San Jose, CA)
    …development, constraints validation, timing analysis and closure. + Experience with formal verification , timing analysis and Eco implementation. + Experience ... clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC). + Drive tools and methodologies to achieve...environment. + Possess ability to learn and adapt to new tools and methodologies on the fly. + Excellent… more
    Broadcom (12/12/25)
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  • Sr Principal Engineer Systems

    Northrop Grumman (San Diego, CA)
    verification + Experience with FMS programs + Experience with formal requirement verification and decomposition + Programming Skills in C/C++/Python/VBA ... the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join...traceability for defects + Develop, de-bug and execute Regression Verification Tests + Perform hands-on Integration within Test environment… more
    Northrop Grumman (11/04/25)
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  • Software Quality Engineer (Level 3)

    Lockheed Martin (Palmdale, CA)
    …performing process, product, supplier, special quality evaluations/audits, and test verification /validation throughout the software development lifecycle as well as ... the software lifecycle \(e\.g\. Requirements, Design, Coding, Unit Testing, Formal Testing, Integration & Testing, Release, Configuration Management, Problem… more
    Lockheed Martin (12/17/25)
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  • Capital Projects Manager, Public Works

    The County of Los Angeles (Los Angeles, CA)
    …and makes recommendations on changes requested by user departments; Coordinates formal and informal design reviews with technical assistance from the Architectural ... limits; Arranges for the timely availability of custom equipment for new facilities; Monitors and coordinates construction supervision and inspection; Authorizes… more
    The County of Los Angeles (10/18/25)
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  • Sr Account Technical Executive II

    Cadence Design Systems, Inc. (San Jose, CA)
    …Must have a deep te c hni c al knowledge and understanding of digital verification flows, including simulation, debug, coverage, formal , and Verification IP. ... the c ore te c hnology requirements in digital verification , leadership for defining and c oordinating disruptive te...acc ount management or as a Appli c ations Engineer or Design Engineer with proven tra… more
    Cadence Design Systems, Inc. (11/18/25)
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  • Regional Operations Manager, Parks And Recreation…

    The County of Los Angeles (Los Angeles, CA)
    …and believe you qualify for this opportunity, please provide verification via official documentation of additional responsibility bonus, out-of-class bonus, ... application submission. Employees do not need to submit such verification if they hold or have held a position...Working to High Quality Standards + Achievement + Generating New Ideas + Willingness to Learn + Empathy +… more
    The County of Los Angeles (12/11/25)
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  • Marine Corps Tactical Systems Support Activity…

    UIC Government Services and the Bowhead Family of Companies (San Diego, CA)
    …Marine Force (FMF) more capable. **Responsibilities** Positions available may include: + Network Engineer , Master + Network Engineer + C2 Network Engineer ... listed on the applicant's resume/application may be subject to verification . Where driving may be required or where a...unless the disclosure is (a) in response to a formal complaint or charge, (b) in furtherance of an… more
    UIC Government Services and the Bowhead Family of Companies (11/10/25)
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  • ASIC Design Technical Leader - Design & Timing…

    Cisco (San Jose, CA)
    …Cadence). + Experience with Spyglass CDC and glitch analysis. + Experience using Formal Verification : Synopsys Formality and Cadence LEC. + Experience with ... customer shipments. **Your Impact** You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding...to $241,200.00 and reflects the projected salary range for new hires in this position in US and/or Canada… more
    Cisco (11/18/25)
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