• Senior Server Firmware Bringup Engineer

    NVIDIA (Santa Clara, CA)
    …is designed and validated for factory use cases. + Working closely with BMC, FPGA , Hardware teams to fulfill these goals. + Partner with security team to ensure ... developed code is in line with product security goals. + Collaborate with QA/Test architects to produce proper test tools and automation for qualifying the whole system software and firmware stack. What we need to see: + Bachelor's Degree or higher in… more
    NVIDIA (10/25/25)
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  • Principal/ Sr Principal Engineer Embedded Software

    Northrop Grumman (San Diego, CA)
    …+ Familiarity with PowerPC architectures and peripherals + Familiarity with VHDL/Verilog/ FPGA + Familiarity with IBM tools (Rhapsody, DOORS, Clearcase) + Familiarity ... with Green Hills AdaMulti + Current active Secret or Top Secret Clearance + Current active SAP clearance + Currently engaged in Networked Information Solutions program portfolio(s) Primary Level Salary Range: $110,300.00 - $165,500.00 Secondary Level Salary… more
    Northrop Grumman (10/23/25)
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  • Senior Embedded Software Developer

    NVIDIA (Santa Clara, CA)
    …kernel modules, device drivers, and user-space applications + Hardware experience ( FPGA development, reading schematics) + Experience using CMake, Python + Video ... and/or audio signal processing background + Linux experience (kernel modules, device drivers, user-space applications) NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and… more
    NVIDIA (10/21/25)
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  • DSP or Serdes RTL Sr Principal Digital Design…

    Cadence Design Systems, Inc. (San Jose, CA)
    …communication skills and be self-motivated and well organized. + Experience with FPGA and/or emulation platform is a plus. + Firmware development of embedded ... microcontroller systems is a plus. Substantial experience with Verilog is required, as are excellent logic and debug skills. Engineering expertise in mixed-signal IP development procedures and Ethernet connectivity protocol knowledge are also strongly… more
    Cadence Design Systems, Inc. (10/17/25)
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  • Senior Component Engineer

    Palo Alto Networks (Santa Clara, CA)
    …is a huge plus. + Demonstrated broad technical competence in multiple technologies (ASIC, FPGA , Comm IC, Processor, SSD) with expert level experience in one or more ... area is required. + Proven knowledge of failure mechanisms in semiconductor and system level component interaction and assemblies over a wide range of technologies. + Demonstrated technical and operational problem solving and solution implementation skills in… more
    Palo Alto Networks (10/16/25)
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  • Electrical Engineer, ALG, Amazon Leo Government

    Amazon (Northridge, CA)
    …circuits including Analog Power, Digital Design, Mixed-Signal ADC/DAC, Processors, FPGA , MCU, SoC, Memory, Transceivers, Clock generation and distribution. Analyze ... designed circuits using software tools for performance and characterization including Signal Integrity (SI) and Power Integrity (PI) on fabricated Printed Circuit Board (PCB) designs. Identify top level customer requirements and ensure high quality and… more
    Amazon (10/15/25)
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  • Principal R&D Engineer

    Silvus Technologies (Los Angeles, CA)
    …design, simulation, and verification work. + Overseeing relevant simulation, software, FPGA , and testing efforts. + Customer-facing engagement and technical material ... preparation when needed. + Reporting to management, as required for strategic planning and assessment. + Participate in Research and Development business development and capture efforts to include: + Whitepaper and proposal preparation. + Understand current… more
    Silvus Technologies (10/15/25)
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  • SystemVerilog/UVM Design Verification Engineer

    US Tech Solutions (Goleta, CA)
    …tasks. **Experience:** + 5-8 years of experience in Pre-Silicon Design Verification ( FPGA or ASIC). + Strong proficiency in SystemVerilog and UVM (must be ... able to work independently). + Experience with functional and code coverage closure, assertion-based verification, and debugging complex designs. + Hands-on experience with PCIe, AXI4, and processor/SoC-related flows. + Solid understanding of simulation… more
    US Tech Solutions (10/14/25)
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  • Senior Applications Engineer - DDR Design IP

    Cadence Design Systems, Inc. (San Jose, CA)
    …Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA design* Knowledge of AXI, DFI protocols* Working knowledge of memory controller and ... memory PHY The annual salary range for California is $84,000 to $156,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation… more
    Cadence Design Systems, Inc. (10/11/25)
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