• Senior Verification Engineer

    Microsoft Corporation (San Diego, CA)
    …across Microsoft cloud hardware. We are seeking a motivated **Senior** ** Verification Engineer ** who is enthusiatic about cutting-edge hardware acceleration ... + 3 years of developing UVM-based testbenches or completion of formal design verification (DV) training. **Other Requirements:** Ability to meet Microsoft,… more
    Microsoft Corporation (10/31/25)
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  • Senior Verification Engineer

    Microsoft Corporation (San Jose, CA)
    …testing, and deploying networking acceleration on Azure, and the largest deployment of Field-Programmable Gate Array ( FPGA ) SmartNICs (Azure Boost) ... millions of people across the planet. As a Senior Verification Engineer in the Accelnet Hardware team,...equivalent experience. + 5+ years technical experience in hardware design verification , verification methodologies, or… more
    Microsoft Corporation (10/28/25)
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  • Sr. ASIC Design Engineer (Silicon…

    SpaceX (Irvine, CA)
    Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're...top level and deliver the fully verified, synthesis/timing clean design + Work closely with verification team… more
    SpaceX (08/22/25)
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  • Digital Design Engineer

    Meta (San Diego, CA)
    **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital ... our industry leading virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block… more
    Meta (10/30/25)
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  • Digital Design Engineer

    Meta (Sunnyvale, CA)
    **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a industry-leading group of researchers and engineers, and use your digital ... ICs to drive our industry leading wearable systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block level… more
    Meta (10/18/25)
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  • Senior Memory Controller Verification

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking hardworking, motivated and creative Senior Verification Engineer for our Tegra SoC Memory Subsystem IP verification Team! At NVIDIA, we ... which you will verify. + Work with and enable FPGA and software teams to ensure that software is...MS or equivalent experience. + 3+ years of ASIC verification experience of complex design units displaying… more
    NVIDIA (10/02/25)
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  • Electrical Design Validation…

    Capgemini (Santa Clara, CA)
    **About the Job You're Considering** + Test and bring-up FPGA and CPU based boards and systems + Review system specification documents for architecture, electrical, ... delivery, thermal, and mechanical requirements + Work closely with in-house board design teams and external contractors to guide and review schematic, layout,… more
    Capgemini (09/27/25)
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  • Staff Hardware Systems Design

    Google (Sunnyvale, CA)
    Staff Hardware Systems Design Engineer , Board and Systems _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Advanced** Experience owning outcomes and decision ... 6 years of experience working in a hardware systems design , or 5 years of experience with an advanced...goals are met with systems and will work with ASIC/ FPGA , Software, and Verification teams to ensure… more
    Google (10/22/25)
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  • Electrical Design Engineer

    Micron Technology, Inc. (San Jose, CA)
    …the world to learn, communicate and advance faster than ever. As an Electrical Design Engineer in the Systems Integration Group SIG at Micron Technology, you ... and electronic load instruments. **What Sets You Apart:** + Familiarity with digital design including microcontrollers and FPGA devices + Understanding of common… more
    Micron Technology, Inc. (10/27/25)
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  • Senior Applications Engineer - DDR…

    Cadence Design Systems, Inc. (San Jose, CA)
    …Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA design * Knowledge of AXI, DFI protocols* Working knowledge of memory controller ... to make an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San Jose, CAJob DescriptionThe Cadence IP team develops… more
    Cadence Design Systems, Inc. (10/11/25)
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