- US Tech Solutions (Goleta, CA)
- …independently and take ownership of verification deliverables within a UVM /SystemVerilog environment. + The engineer will collaborate with design, ... **Job Description:** + The Verification Engineer will contribute to the... prior to tape-out. **Responsibilities:** + Perform pre-silicon functional verification of digital designs using UVM and… more
- The Boeing Company (El Segundo, CA)
- …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC/ FPGA Verification Engineer on the Boeing Electronic Products team ... units designed at other sites. **Position Responsibilities:** + Design and implement an ASIC/ FPGA verification environment utilizing UVM & System Verilog. +… more
- BAE Systems (San Diego, CA)
- …may be available based on position level and/or job specifics. **Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)** **117193BR** EEO ... your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan,...SystemVerilog/ UVM , OVM, and/or VHDL + Experience with FPGA /ASIC design and verification tools (Mentor Questa… more
- The Boeing Company (Mountain View, CA)
- …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC/ FPGA Engineer on the Boeing Electronic Products team you will develop ... & Weapons Systems has an exciting opportunity for multiple **ASIC and/or FPGA Design and Verification Engineers** (Entry Level, Associate, or Experienced)… more
- Northrop Grumman (San Diego, CA)
- …+ Experience with AMD FPGAs and the Vivado tool + Experience with OVM/ UVM Verification methodologies + Demonstrated ability to translate system performance and ... individuals within our Software organization located in **Rancho Bernardo, CA** . As an FPGA design engineer you will design, implement and verify HDL to manage… more
- Cisco (Milpitas, CA)
- …leading FPGA devices and tools. **Preferred Qualifications** + Experience with UVM and/or VMM Verification methodology. + Experience with high-speed design ... networking system requirements, mapping them into functional blocks for FPGA implementation, working with the cross functional team to...ASR8000 routers. You will be a member of the FPGA team that designs control path FPGAs for the… more
- Broadcom (San Jose, CA)
- …verification tasks such as: verification environment development using modern verification techniques (System Verilog and UVM ); designing verification ... flows and DV methodologies + Strong working knowledge of object oriented verification languages (OVM, UVM , etc.), C/C++, Perl, and scripting skills. +… more
- Microsoft Corporation (Mountain View, CA)
- …will manage and optimize the Cloud infrastructure. We are looking for a **Senior Verification Engineer ** to join the team. **Responsibilities** The role will be ... verification methods + Experience in RTL design for FPGA or emulation + Experience in Assembly, startup code...with test plan definition + Substantial background in creating UVM Test Benches, developing tests, and debugging designs +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Verification Engineer ! NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 ... partner with ASIC design engineers, IP architects and other verification engineers to formalize product features + Verify IP's...product features + Verify IP's using System Verilog and UVM + Build testbenches and enhance flows for automation… more
- Teledyne (Milpitas, CA)
- …+ Integrate PCIe IP cores, DMA engines, and custom protocol decoders. + ** Verification & Debug** + Build SystemVerilog/ UVM testbenches for block and system-level ... We are looking for a top-notch Staff Logic Design engineer who has the right composition of knowledge, experience,...for protocol capture, analysis, and emulation. You'll work on FPGA -based systems that decode and analyze High speed protocols… more