• Design Verification Engineer

    Amazon (Sunnyvale, CA)
    …and satellite bus FPGAs A day in the life Kuiper Production team FPGA verification engineer . Create UVM verification simulation solutions. The ... Description Kuiper Production team FPGA Verification engineer . Creating...will work with design and systems teams to define/develop/implement/test/release UVM test environments in order to verify FPGA more
    Amazon (07/05/25)
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  • ASIC and/or FPGA Design…

    The Boeing Company (Huntington Beach, CA)
    …Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems). As an ASIC/ FPGA Engineer on the Boeing Electronic Products team you will develop ... Intelligence & Weapons Systems has an exciting opportunity for multiple **ASIC and/or FPGA Design and Verification Engineers (Lead, Senior or Principal)** to… more
    The Boeing Company (09/25/25)
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  • Senior Principal Design Verification

    BAE Systems (San Diego, CA)
    …may be available based on position level and/or job specifics. **Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)** **113449BR** EEO ... your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan,...SystemVerilog/ UVM , OVM, and/or VHDL + Experience with FPGA /ASIC design and verification tools (Mentor Questa… more
    BAE Systems (09/09/25)
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  • Senior Design Verification Engineer

    Amazon (Sunnyvale, CA)
    UVM , assertions and coverage driven verification . Experience using multiple verification platforms: UVM test bench, FPGA , emulator, software ... of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on...with design engineers and architects Create and enhance constrained-random verification environments using SystemVerilog and UVM Write… more
    Amazon (09/04/25)
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  • Senior ASIC Verification Engineer

    Tarana Wireless (Milpitas, CA)
    …will make such an impact on our products. We are looking for a Senior ASIC Verification Engineer that is self driven however knows when to collaborate to solve ... generation SoCs + Work with system architects, RTL designers, FPGA and emulation engineers to ensure that verification...+ BSEE required/MSEE preferred + 5-12 years of related Verification experience + Strong knowledge of UVM more
    Tarana Wireless (09/25/25)
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  • ASIC Design Verification Engineer

    Amazon (San Diego, CA)
    …program . Write tests in C/C++ to execute on embedded CPU . Develop tests for FPGA and emulation platforms . Run formal verification of complex blocks to ensure ... and communication systems team and participate in system level verification using test benches constructed using UVM ,...level verification using test benches constructed using UVM , System C and DPI-C . Develop a highly… more
    Amazon (08/08/25)
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  • Staff ASIC Design Verification

    Google (Mountain View, CA)
    Staff ASIC Design Verification Engineer , Platforms and Devices + _link_ Copy link + _email_ Email a friend _corporate_fare_ Google _place_ Mountain View, CA, USA ... at RTL and GLS level using SystemVerilog or C/C++ or Universal Verification Methodology ( UVM ). + Experience with system-level architecture, scripting languages,… more
    Google (10/01/25)
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  • Senior Verification Engineer

    Microsoft Corporation (Mountain View, CA)
    …will manage and optimize the Cloud infrastructure. We are looking for a **Senior Verification Engineer ** to join the team. **Responsibilities** The role will be ... verification methods + Experience in RTL design for FPGA or emulation + Experience in Assembly, startup code...with test plan definition + Substantial background in creating UVM Test Benches, developing tests, and debugging designs +… more
    Microsoft Corporation (09/20/25)
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  • Senior IP Verification Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Verification Engineer ! NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 ... partner with ASIC design engineers, IP architects and other verification engineers to formalize product features + Verify IP's...product features + Verify IP's using System Verilog and UVM + Build testbenches and enhance flows for automation… more
    NVIDIA (09/23/25)
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  • ASIC Verification Engineer

    Amazon (Sunnyvale, CA)
    …in areas of image processing. - Familiarity with Matlab - Familiarity with formal verification techniques - Lab debug experience and/or FPGA debug - Strong ... silicon into Blink and Ring battery powered devices. Our verification team works on state-of-the art SoCs in a...TCL) - 5+ years experience in System Verilog or UVM Preferred Qualifications - Master's or PH.D in Computer… more
    Amazon (09/10/25)
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