• ASIC Design Verification Engineer…

    Amazon (Cupertino, CA)
    …our customers use for accelerated computing through Machine Learning acceleration and FPGA acceleration. If you are interested in "building a complete product" from ... May 2023 and December 2025 Programming experience in System Verilog or UVM Preferred Qualifications Master's or PhD in Electrical Engineering or Computer Engineering… more
    Amazon (09/16/25)
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  • Digital Design Engineer

    Meta (San Diego, CA)
    **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design ... virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block level uArchitecture… more
    Meta (08/01/25)
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  • Emulation Engineer II

    Microsoft Corporation (Santa Clara, CA)
    …on Chip (SoC) emulation verification with System Verilog (SV)/Universal Verification Methodology ( UVM ) environments using any Standard Emulator (Palladium, ... significantly superior performance compared to CPU-based alternatives **Responsibilities** As an Emulation Engineer II in the Data Processing Unit team you will be… more
    Microsoft Corporation (09/23/25)
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