• Principal / Senior Principal FPGA /ASIC…

    Northrop Grumman (Linthicum Heights, MD)
    …+ Experience with FPGA or ASIC + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting languages (Bash, Perl, Python, ... for both are listed below:** **Basic Qualifications Principal Digital Verification Engineer :** + Bachelor's degree in a... FPGA or ASIC + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting… more
    Northrop Grumman (11/06/25)
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  • Senior FPGA Development Engineer

    Amazon (Jessup, MD)
    …Web Services (AWS) connectivity and is looking for help. AWS seeks a Senior FPGA Development Engineer with experience developing programmable logic on the most ... Electrical Engineering or a related field - Knowledge of UVM and Matlab - Experience in communication theory, OFDM,...power, area analysis and trade-offs - Experience with modern ASIC/ FPGA design and verification tools - Experience… more
    Amazon (10/10/25)
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  • Senior FPGA Design Engineer - remote…

    GE Aerospace (Baltimore, MD)
    …sustainable flight and believe in our talented people to make it happen. The Senior FPGA Design Engineer will play a critical role in designing, developing, and ... into cutting-edge aerospace products. Your expertise in digital design, verification , and FPGA /ASIC development will contribute to...Libero and Xillinx Vivado. + Experience in VHDL and UVM Test Benches. + Experience with the Mentor Graphics… more
    GE Aerospace (11/13/25)
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  • Principal Digital Verification

    Northrop Grumman (Linthicum Heights, MD)
    …DoD secret clearance and Special Program Access (SAP). + 3 years of experience with FPGA or ASIC verification using UVM + Experience developing testplans, ... you to join our team as a Principal Digital Verification Engineer /Senior Principal Digital Verification ...Program Access (SAP). + 3 years of experience with FPGA or ASIC verification using UVM more
    Northrop Grumman (10/03/25)
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  • Staff Lead Design Verification

    Northrop Grumman (Annapolis Junction, MD)
    …culture of design. We are seeking an exceptional Senior Functional Verification Engineer specializing in ASIC and FPGA technologies. The ideal candidate will ... in gate timing requirements + Develop comprehensive Universal Verification Methodology ( UVM ) simulation environments **Collaborative Processes:** + Work… more
    Northrop Grumman (10/16/25)
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  • Staff Digital Verification Engineer

    Northrop Grumman (Annapolis Junction, MD)
    …work will be done 100% onsite in Linthicum, MD._** **Basic Qualifications Staff Digital Verification Engineer :** + Bachelor's degree in a technical area (BSEE or ... able to obtain and maintain a security clearance.** **Preferred Qualifications Staff Digital Verification Engineer :** + Advanced Degree either MS or PhD +… more
    Northrop Grumman (08/27/25)
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  • Senior Digital Verification Engineer

    Huntington Ingalls Industries (Fort Meade, MD)
    …Matlab, etc. * UVM concepts * Directed, constrained-random, and assertion-based verification (ABV) techniques at the gate , interface, and transaction levels, ... can uncover difficult-to-activate corner-case bugs and vulnerabilities in the gate -level netlists of FPGA and ASIC designs....Software or hardware reverse-engineering (eg, IDA Pro, Ghidra) * FPGA design or verification * Familiarity with… more
    Huntington Ingalls Industries (10/09/25)
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  • Senior Test and Integration Engineer

    Leidos (Linthicum, MD)
    … and testing of new ASIC designs prior to fabrication using Field Programmable Gate Arrays ( FPGA ) to emulate the chips. + (U//FOUO) Write custom interfaces ... is currently looking to add a Test and Integration Engineer to a Cyber Security Program near Ft. Meade,...(COTS) software and Mentor Graphics products. + Use advanced verification methodologies using industry standard UVM (Unified… more
    Leidos (11/07/25)
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