• Design Verification Engineer

    Meta (Sunnyvale, CA)
    …from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement ... test benches for block, IP, sub-system, and SoC level verification 2. Develop functional tests based on verification...verifying ARM/RISC-V based sub-systems and SoCs 14. Experience verifying CPU/ GPU designs 15. Experience in one or more of… more
    Meta (11/08/25)
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  • Senior Circuit Verification Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior Circuit Verification Engineer to join our dynamic and growing team. Designing RAMs at leading edge process nodes ... forefront of transforming how the world computes-from pioneering the GPU in 1999 to powering today's AI revolution. We're...of innovative circuits. + Support designer efforts in running formal verification , electronic rule checking, and other… more
    NVIDIA (09/09/25)
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  • Senior ASIC Design Engineer - DFX

    NVIDIA (Santa Clara, CA)
    …Strong proficiency in micro-architecture and RTL development using Verilog. + Experience with formal verification using JasperGold is a plus. + Deep expertise in ... We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over...reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC… more
    NVIDIA (10/25/25)
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  • Senior SRAM Engineer , Circuit Design

    NVIDIA (Santa Clara, CA)
    …using various flows and methodologies including: Static Timing analysis, EM and IR analysis, Formal Verification At NVIDIA, we have been at the forefront of ... We are now looking for a Senior SRAM Engineer ! The Full Custom Macro team at NVIDIA...for over two decades. Our groundbreaking invention of the GPU in 1999 fueled the growth of PC gaming… more
    NVIDIA (10/03/25)
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  • RTL Design Engineer , Multimedia…

    Google (Mountain View, CA)
    …Level (RTL) coding, function/performance simulation debug and Lint/Clock Domain Crossing (CDC)/ Formal Verification (FV)/Unified Power Format (UPF) checks. + ... RTL Design Engineer , Multimedia and Machine Learning Accelerators _corporate_fare_ Google...on computer architecture. + Experience implementing Graphics Processing Unit ( GPU ), Multimedia Intellectual Property (IP)(Camera, Display or COdec) or… more
    Google (11/20/25)
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