• ASIC Design Engineer

    Broadcom (San Jose, CA)
    …static timing analysis. You will either be responsible for block and/or chip level design and integration. Job Requirements BSEE/MSEE. Minimum 8 years of ... in mapping communications algorithms or standards (802.3 Ethernet) to hardware and understanding of system design tradeoffs...Ethernet) to hardware and understanding of system design tradeoffs for high volume applications. Must have good… more
    Broadcom (07/26/25)
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  • FPGA Design Engineer

    Tarana Wireless (Milpitas, CA)
    …and validate logic at both module and system levels + Participate in system- level integration and troubleshooting + Collaborate across hardware and software ... minds in the industry. If you're passionate about digital design , solving complex problems, and building products that make...you've been waiting for. As part of our FPGA Design Team, you'll contribute to the development and testing… more
    Tarana Wireless (09/17/25)
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  • DSP or Serdes RTL Sr Principal Digital…

    Cadence Design Systems, Inc. (San Jose, CA)
    …the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware , and intellectual property to ... and developing flows at all phases of the digital design and functional verification. It is further expected that...may vary based on factors such as qualifications, skill level , competencies and work location. Our benefits programs include:… more
    Cadence Design Systems, Inc. (07/18/25)
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  • Antenna Design Engineer

    Leidos (San Diego, CA)
    …mechanical, electrical, and RF engineering concepts. **Primary Responsibilities:** + Hands-on design and realization of both front and back-end antenna systems and ... RF components, and RF systems. + Use of computational electromagnetic software to design and predict performance on various types of antennas and apertures (HFSS,… more
    Leidos (08/29/25)
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  • DFT Design Engineer , AWS Machine…

    Amazon (Cupertino, CA)
    …a member of the Silicon Optimization Engineering Team you'll be responsible for the design and optimization of hardware in our data centers. You'll provide ... possible today. Key job responsibilities * Develop, implement and verify state-of-the-art Design for Test (DFT) architectures * Work with block designers to… more
    Amazon (08/04/25)
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  • Propulsion Engineer (Raptor Combustion…

    SpaceX (Hawthorne, CA)
    …execution. Collaborate with engineers from other teams to design and develop hardware that meets high level engine objectives + Identify, organize, and drive ... the largest launch vehicle in history. RESPONSIBILITIES + Own the success of hardware design and requirements, delivery of production at target throughput rates,… more
    SpaceX (07/26/25)
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  • Propulsion Engineer (Raptor Development…

    SpaceX (Hawthorne, CA)
    …operations tasks for Raptor ignition and transients + Own the success of hardware design and requirements, delivery of production at target throughput rates, ... high- level engine and vehicle objectives. + Identify, organize, and drive hardware design and sequence changes related to departmental priorities such as… more
    SpaceX (09/18/25)
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  • Digital FPGA Engineer Level 4 (AHT)

    Northrop Grumman (Los Angeles, CA)
    level requirements, review designs and analysis. **Basic Qualifications Digital FPGA Engineer Level 4:** + Bachelor's degree in electrical engineering or ... The selected individual will work on FPGA and ASIC Design across the full product life cycle process. In...DoD Secret Clearance to start **Preferred Qualifications Digital FPGA Engineer Level 4:** + Proficient in DSP… more
    Northrop Grumman (09/07/25)
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  • Digital FPGA Engineer Level 3 (AHT)

    Northrop Grumman (Acton, CA)
    level requirements, review designs and analysis. **Basic Qualifications Digital FPGA Engineer Level 3:** + Bachelor's degree in electrical engineering or ... The selected individual will work on FPGA and ASIC Design across the full product life cycle process. In...DoD Secret Clearance to start **Preferred Qualifications Digital FPGA Engineer Level 3:** + Experience with DSP,… more
    Northrop Grumman (09/25/25)
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  • Principal or Senior Principal HPC Engineer

    Northrop Grumman (Redondo Beach, CA)
    …shorter amounts of time-enabling our engineering teams to successfully and timely design , optimize, and validate the future of LO platforms. They will also ... performance. + Manage HPC systems throughout their life cycle: concept, design , fabrication, test, installation, operation, maintenance, and disposal. + Perform HPC… more
    Northrop Grumman (09/13/25)
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