• Senior Business Development Manager - AI…

    Micron Technology, Inc. (San Jose, CA)
    …US-based supplier of cloud memory technologies, including DDR, LPDDR, and High-Bandwidth Memory ( HBM ). HBM is a foundational technology that is powering the ... define and prioritize features for future generations of High Bandwidth Memory ( HBM ) products. + **Portfolio Alignment** : Ensure Micron's memory solutions are… more
    Micron Technology, Inc. (11/26/25)
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  • Global Commodity Manager, Memory

    Google (Sunnyvale, CA)
    …to drive the Joint Electron Device Engineering Council (JEDEC) standard high-bandwidth memory ( HBM ), Custom HBM and server memory technologies at key memory ... suppliers. + Be conversant with the integration aspects of HBM with AI/ML accelerator SoCs by ASIC houses/OSATs. + Maintain a level of industry and technology… more
    Google (12/04/25)
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  • Staff Logic Circuit Design Engineer

    Micron Technology, Inc. (Folsom, CA)
    …inspiring the world to learn, communicate and advance faster than ever. A HBM RTL designer will need to have significant experience front end digital design! ... + Define requirements, develop specifications, and architect RTL blocks for HBM products. + Own circuit development, simulations, and guide physical layout… more
    Micron Technology, Inc. (11/20/25)
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  • MTS Circuit Design Engineer, HSIO

    Micron Technology, Inc. (Folsom, CA)
    …We are searching for a High Speed I/O Design engineer at our Micron Technology's HBM Team in Folsom, California. As a high speed Design engineer, you will be working ... multiple projects-based environment. **Responsibilities** + Architect high-speed clocking networks for HBM applications in AI and HPC. + Evaluate PLL performance and… more
    Micron Technology, Inc. (11/20/25)
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  • Senior Memory System Engineer

    NVIDIA (Santa Clara, CA)
    …for NVIDIA CPUs and SOCs. What You Will Be Doing: + Analyze future DDR/LPDDR/ HBM technologies to determine optimum performance, power, function and RAS in memory for ... features, ECC algorithm, SI and PI (Training algorithm) in DDR, LPDDR, and HBM . + Strong understanding of memory sub system level interaction with Cache, Memory… more
    NVIDIA (10/02/25)
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  • Sr. SDE, MLA hardware/software co-design,…

    Amazon (Cupertino, CA)
    …drivers * Knowledge in SoC architecture * Knowledge in IO(PCIE, AXI) , Memory( HBM , DDR), CPU architecture and Interconnects. Amazon is an equal opportunity employer ... and does not discriminate on the basis of protected veteran status, disability, or other legally protected status. Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff;… more
    Amazon (12/11/25)
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  • Senior Signal and Power Integrity Engineer…

    NVIDIA (Santa Clara, CA)
    …+ SI work on one or more signaling standards like PCI express, USB, SATA, HDMI, HBM , DDR5, GDDR6, LPDDR5X, etc. + Hands on use of 3-D modeling tools like ANSYS ... HFSS/Q3D, 2.5-D with ANSYS SIWAVE or similar and 2D such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board impairments. + Familiarity with use of VNA, TDR, DSO, ParBERT and use of tools/applications like… more
    NVIDIA (12/09/25)
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  • Lead Design Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …functional validation for next-generation DDR interfaces such as DDR5, LPDDR5, LPDDR6, HBM and GDDR7. + Design and execute innovative testing strategies to ... accelerate post-silicon bring-up. + Transform raw data into actionable insights through advanced analysis and visualization. + Resolve complex issues by driving JIRA-based debug workflows and collaborating across teams. + Deliver high-impact characterization… more
    Cadence Design Systems, Inc. (12/05/25)
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  • Package Design Engineer

    Broadcom (San Jose, CA)
    …base stations. These designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM , DDR5 and more. You'll have the opportunity to collaborate with the team ... to create the package structures needed to enable new design, and contribute to efficiency improvements for our design team. **RESPONSIBILITIES:** + Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity,… more
    Broadcom (12/03/25)
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  • Signal Integrity Engineer

    Broadcom (San Jose, CA)
    …direction with incomplete information. + Knowledge of at least one DDR/LPDDR and/or HBM SI/PI sign-off flow tool suite. + Ability to manage analysis, documentation, ... and presentation roles. + Flexibility to integrate new ideas and tools to enhance signoff capabilities. + Experience with various IC, Package and PCB database types. + TCL, Python scripting experience to automate routine tasks. **Education/Experience:** +… more
    Broadcom (11/26/25)
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