• ASIC/FPGA Design Engineer (SMES)

    L3Harris (Camden, NJ)
    …OS. + Knowledge of PCIe, NVMe, USB protocols. + Experience with High level synthesis (Xilinx Vivado HLS , AND/OR Mentor Calypto ). In compliance ... (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult ( HLS ). This is a key, high impact...Formal, Lint) + Generate test plans + Perform module level verification, synthesis /STA, Lab debug, SW driven… more
    L3Harris (10/12/25)
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