• Senior Member Engineering Staff-ASIC/FPGA Design

    L3Harris (Camden, NJ)
    …OS. + Knowledge of PCIe, NVMe, USB protocols. + Experience with High level synthesis (Xilinx Vivado HLS , AND/OR Mentor Calypto ). In compliance ... (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult ( HLS ). This is a key, high impact...Formal, Lint) + Generate test plans + Perform module level verification, synthesis /STA, Lab debug, SW driven… more
    L3Harris (07/23/25)
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  • Electrical Engineer Intern - FPGA Design (Camden,…

    L3Harris (Camden, NJ)
    …USB + Experience with Xilinx SoC design with SDKs and PetaLinux OS + Experience with High - Level Synthesis ( HLS ) with Vivado HLX or Mentor Catapult + ... L3Harris is dedicated to recruiting and developing high -performing talent who are passionate about what they...+ Implement design in RTL (VHDL) and perform module level simulations + Perform Synthesis , Place and… more
    L3Harris (09/05/25)
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  • FPGA Design Engineer

    Insight Global (Camden, NJ)
    …NVMe, USB Experience with Xilinx SoC design with SDKs and PetaLinux OS Experience with High - Level Synthesis ( HLS ) with Vivado HLX or Mentor Catapult ... like Ethernet, I2C, SPI, and AXI, contributing to secure, high -performance communication products. Key Responsibilities: Design and implement FPGA architectures… more
    Insight Global (09/09/25)
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