• Principal design engineer, VLSI…

    SanDisk (Milpitas, CA)
    …at transistor level and gate level for leading-edge 3D NAND flash memory focusing on high - speed datapath circuit design and page buffers. + Perform block ... chip circuit simulations to meet all performance specifications. + RTL design , synthesis, static timing analysis and...a big advantage PREFERRED: + Knowledge and/or experience in High speed I/O circuit is a big… more
    SanDisk (10/15/25)
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  • Senior Logic Design Engineer- Physical…

    NVIDIA (Santa Clara, CA)
    …industry standard physical design tools is required. + A background in high - speed interconnect/cache physical design is preferred. + Verilog expertise is ... 5+ years of experience in processor or other related high -performance semiconductor designs. + Physical design expertise...required as is a deep understanding of ASIC design flow including RTL design ,… more
    NVIDIA (09/10/25)
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  • Staff Silicon Design Engineer, Raxium

    Google (Fremont, CA)
    …field, or equivalent practical experience. + 10 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog ... Learn more aboutbenefits at Google (https://careers.google.com/benefits/) . **Responsibilities** + Design and develop RTL using SystemVerilog for various… more
    Google (10/07/25)
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  • Sr. ASIC Design Engineer (Silicon…

    SpaceX (Irvine, CA)
    …bus protocols (eg AXI, AHB, etc.) + Experience with embedded processors + Experience with high speed and low power design techniques + Scripting skills ... Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX...requirements and system limitations + Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level… more
    SpaceX (08/22/25)
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  • Senior Engineer - Design for Test (DFT)

    Microsoft Corporation (Mountain View, CA)
    …operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners ... Manufacturing Engineering** _(CSME)_ organization within _SCHIE_ is responsible for design , development, manufacturing and packaging of Microsoft's state-of-the-art computer… more
    Microsoft Corporation (10/28/25)
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  • SystemVerilog/UVM Design Verification Test…

    US Tech Solutions (Goleta, CA)
    …SystemVerilog and UVM, a strong understanding of processor architectures, and high - speed protocols. **Responsibilities:** + Architect, develop, and maintain ... We are seeking a highly skilled and meticulous SystemVerilog/UVM Design Verification Test Engineer to play a crucial role...blocks, with a focus on ARM processor subsystems and high - speed interfaces. + Implement test cases and… more
    US Tech Solutions (10/14/25)
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  • Physical Design Flow and Methodology Lead

    Google (Sunnyvale, CA)
    …low-power implementation (UPF/CPF). + Experience in integrating and ensuring closure for high - speed IP subsystems. + Experience with evaluating foundry process ... to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL / design tradeoffs for physical design closure. +… more
    Google (10/24/25)
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  • Design Engineering Director

    Cadence Design Systems, Inc. (San Jose, CA)
    … Printed circuit boards in Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and Power integrity ... to make an impact on the world of technology. Design Engineering Director -HPP The role will be a...Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/ PCIe/CXL/UCIe/ *… more
    Cadence Design Systems, Inc. (10/07/25)
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  • ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …position, you will have the opportunity to be responsible for the micro-architecture and design including RTL design , synthesis and timing analysis using ... NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team!...years of relevant industry experience and a background in high - speed coherent interconnects, protocol bridges, hardware-managed coherency… more
    NVIDIA (10/25/25)
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  • Senior ASIC Design Engineer, Project Kuiper

    Amazon (San Diego, CA)
    …a constellation of Low Earth Orbit satellites that will provide low-latency, high - speed broadband connectivity to unserved and underserved communities around the ... customer requirements and wireless system teams to define modems, high - speed interfaces, embedded processors, and DSP solutions...in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level… more
    Amazon (10/08/25)
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