• MTS Memory Sustaining Design Engineer, HBM

    Micron Technology, Inc. (Richardson, TX)
    …innovation and problem-solving in high -performance memory development. + Good experience with RTL Design flow, in DRAM process or Foundry process. + Prior ... + In depth technical expertise in one or more areas - memory array design , high - speed clocking and interface development, logic and custom circuit design… more
    Micron Technology, Inc. (09/28/25)
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  • Physical Design Manager

    Cadence Design Systems, Inc. (Austin, TX)
    …+ Physical verification (DRC/LVS) + Understanding of DFT + Expertise in high speed interconnect Qualifications + Master's degree in Electrical Engineering, ... design flow. In this role you will drive RTL to GDS flow for microprocessor design ,... or related field, including multiple tape outs with high end Arm cores + Proven experience in leading… more
    Cadence Design Systems, Inc. (09/24/25)
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  • Design Verification Engineer

    Amazon (Austin, TX)
    …a constellation of Low Earth Orbit satellites that will provide low-latency, high - speed broadband connectivity to unserved and underserved communities around the ... team works with customer requirements and wireless system teams to define modems, high - speed interfaces, embedded processors, and DSP solutions in latest CMOS… more
    Amazon (09/27/25)
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  • Sr. CAD Engineer, ASIC

    Amazon (Austin, TX)
    …launch a constellation of Low Earth Orbit satellites that will provide low-latency, high - speed broadband connectivity. Come work at Amazon! The Role: As Senior ... Develop, regress, and deploy digital front end flows including RTL static checks and design verification methodology...end flows including RTL static checks and design verification methodology - Develop, regress and deploy digital… more
    Amazon (09/05/25)
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  • Lead Firmware Engineer

    Cadence Design Systems, Inc. (Austin, TX)
    …configurations and specifications. * Relevant experience in developing bare-metal firmware for High - speed SerDes or Memory interface Physical Layer blocks. * ... part of the Cadence DDR PHY IP Front End Design team responsible for - * Develop firmware for...firmware-hardware co-verification plan. * Develop and Debug firmware in RTL based hardware simulations (C +Verilog simulations) * Develop… more
    Cadence Design Systems, Inc. (08/19/25)
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  • ASIC Engineer, Emulation

    Meta (Austin, TX)
    …**Required Skills:** ASIC Engineer, Emulation Responsibilities: 1. Deliver high -quality emulation and prototyping models on industry-standard emulation and ... prototyping platforms 2. Design , build, and execute comprehensive emulation test plans to...USB, and other interfaces on emulation components such as speed bridges, transactors, and virtual components 6. Continuously improve… more
    Meta (10/20/25)
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