- Cisco (San Jose, CA)
- …and ultra-long haul telecommunication networks. **Meet the Team** We are Mixed-signal IC design group that develops high speed ()25Gb/s), and high accuracy, analog ... mentor team members and track deliverables, participate in peer review of complex IC designs and provide solid design methodology from conception to production. *… more
- Broadcom (San Jose, CA)
- …Sign-In before you apply.** **Job Description:** Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group. This position ... Synthesis + Floor-planning and Layout + Flow and Methodology Development + Collaborating with IC Design RTL Engineers + Must work in person at our San Jose site:… more
- Broadcom (Irvine, CA)
- …Lint checks, RTL/gate level simulations & silicon debugging + scripting for various IC design tasks such as STA, equivalency checks, silicon debug etc. + prepare ... Lint checks, RTL/gate level simulations & silicon debugging + scripting for various IC design tasks such as STA, equivalency checks, silicon debug etc. + prepare… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …fundamentals, and Static Timing Analysis is required + Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, ... Science/Engineering, Electrical, Engineering, or related field + Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis,… more
- Broadcom (San Jose, CA)
- …physical design flow and make it more efficient. + Expertise on low power IC design is desirable. + Good knowledge on physical verification using Mentor's Calibre ... tool. Minimum requirements: Bachelor's degree and 8+ years of related experience or Master's degree with 5+ years of experience. **Additional Job Description:** **Compensation and Benefits** The annual base salary range for this position is $120,000 - $192,000… more
- Broadcom (Irvine, CA)
- …Lint checks, RTL/gate level simulations & silicon debugging + scripting for various IC design tasks such as STA, equivalency checks, silicon debug etc. + prepare ... block level resource requirements & development schedule + generate test plans for post silicon validation **Job Requirement:** + _B.S degree in EE or computer Engineering and 5+ years of related experience_ + _M.S degree/Ph.D in EE or Computer Engineering and… more
- Broadcom (San Jose, CA)
- …and flow customization. + Ability to work with cross-functional teams including IC design engineers, packaging egineers, and foundries Additional Skills: + Strong ... problem-solving skills and attention to detail. + Excellent communication and teamwork skills. + Ability to document design processes, specifications, and reviews. + Familiarity with 3DBlox interposer modelling language is a plus Preferred Qualifications: +… more
- Broadcom (Irvine, CA)
- …Account, please Sign-In before you apply.** **Job Description:** **Job Description: IC Design Engineer** + Participate in IP level architectural definition including ... micro-architecture definition + Perform RTL design using Verilog HDL, with an emphasis on performance and area + Implement multi-power and low-power designs + Analyze and resolve Lint and Clock/Reset Domain crossing issues in the design + Collaborate with… more
- CVS Health (Sacramento, CA)
- …Oak Street Health is a rapidly growing company of community-based healthcare centers delivering a new model of care for adults on Medicare. By providing comprehensive ... and integrated care, we improve outcomes, manage costs, and offer an unmatched experience for our patients. As a Senior Product Manager, you will be a key leader in our organization, responsible for driving the strategy and execution for a core part of our… more
- Broadcom (San Jose, CA)
- …**Job duties include:** + Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features. + Architect and develop scalable ... and re-usable testbenches, using the framework of the verification methodology + Build pseudo-random tests to verify and get to full Functional coverage + Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps +… more